JPS62105627U - - Google Patents
Info
- Publication number
- JPS62105627U JPS62105627U JP19807585U JP19807585U JPS62105627U JP S62105627 U JPS62105627 U JP S62105627U JP 19807585 U JP19807585 U JP 19807585U JP 19807585 U JP19807585 U JP 19807585U JP S62105627 U JPS62105627 U JP S62105627U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- output signal
- gate
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は第１図の実施例の各部のタイムチヤート
、第３図は本考案の他の実施例を示すブロツク図
、第４図は本考案の更に他の実施例を示すブロツ
ク図。
符号の説明、１−１〜１−３…１−ｎ……Ｄ―
フリツプフロツプ、２……アンドゲート、３，４
……Ｄ―フリツプフロツプ。
FIG. 1 is a block diagram showing an embodiment of the present invention.
2 is a time chart of each part of the embodiment of FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing still another embodiment of the present invention. Explanation of symbols, 1 -1 to 1 -3 ...1 -n ...D-
Flip flop, 2...and gate, 3, 4
...D-Flip Flop.
Claims (1)
トされるように接続されたｎ個のフリツプフロツ
プと、 該ｎ個のフリツプフロツプのうちの第１番目か
ら（ｎ―１）番目の同一極性の出力端子の各の出
力信号と、ｎ番目のフリツプフロツプの前記極性
に対して逆極性の出力端子の出力信号との論理積
をとるゲートと、 該ゲートの出力信号によつて起動させ、クロツ
ク同期微分出力を発生する（ｎ＋１）個目のフリ
ツプフロツプを設けたことを特徴とする同期微分
回路。[Scope of Claim for Utility Model Registration] n flip-flops connected so that data is shifted to the next stage each time a clock is input, and the first to (n-1) of the n flip-flops. a gate for ANDing each output signal of the same polarity output terminal of the nth flip-flop with the output signal of the output terminal of the nth flip-flop having the opposite polarity; and activated by the output signal of the gate. 1. A synchronous differential circuit characterized in that an (n+1)th flip-flop is provided for generating a clock-synchronous differential output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19807585U JPS62105627U (en) | 1985-12-23 | 1985-12-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19807585U JPS62105627U (en) | 1985-12-23 | 1985-12-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62105627U true JPS62105627U (en) | 1987-07-06 |
Family
ID=31158428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19807585U Pending JPS62105627U (en) | 1985-12-23 | 1985-12-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62105627U (en) |
-
1985
- 1985-12-23 JP JP19807585U patent/JPS62105627U/ja active Pending
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