JPH11175398A - Memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process a program in real time without forming a transfer period from outside even in the case that a program capacity exceeds the capacity of a memory device in a configuration of the memory device for which plural processors and a readable and writable instruction memory are connected. SOLUTION: By preserving a program in a processor 2 with a memory shortage in a memory device 31 of other processor 1 with a free area 41 in an opposite direction from the end to the head, even a program exceeding the capacity of a built-in memory 32 is processed in real time without turning the processor 2 to an operation stop state, thus the free area 41 of the other built-in memory 31 is effectively utilized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device in which a plurality of processors and a readable and writable instruction memory corresponding to each processor are connected to one semiconductor chip.

[0002]

2. Description of the Related Art Hereinafter, a conventional memory device in which a plurality of processors and a readable and writable instruction memory corresponding to each processor are connected to one semiconductor chip will be described.

FIG. 5 is a block diagram of a conventional memory device of this kind. 5, reference numerals 1 and 2 denote processors, 5 denotes a bus arbitration circuit, 11 and 12 denote system buses connecting the processors 1 and 2 and the bus arbitration circuit 5, 31 denotes a built-in memory for storing a program of the processor 1, 41 Is a free area that is an invalid area in the built-in memory 31, and 32 is
A built-in memory in which a program for the processor 2 is stored,
Reference numeral 42 denotes a free area which is an invalid area in the built-in memory 32, and 21 and 22 denote bus arbitration circuits 5 and the built-in memory 3.
This is a system bus connecting the first and second devices. 70 is an external memory in which programs to be written in the internal memories 31 and 32 are stored in advance, 71 is a controller that reads and writes data from and to the external memory 70, 15 is a system bus that connects the external memory 70 and the controller 71, 16
Is a system bus connecting the controller 71 and the bus arbitration circuit 5. One semiconductor chip is constituted by components other than the external memory 70.

The operation of the memory device configured as described above will be described below. First, the processors 1 and 2
To a reset state or an operation stop state such as a halt state. The programs of the processors 1 and 2 are written in the external memory 70 in advance. This program is transferred to the system bus 1 by using a high-speed data transfer function of the controller 71 which is generally called a DMA transfer.
5, 16; the bus arbitration circuit 5; Similarly, the built-in memory 3
2 is written through the system bus 15, the controller 71, the system bus 16, the bus arbitration circuit 5, and the system bus 22. At this time, the built-in memory 3
The word length, which is the bit width, is usually a multiple of 8 bits because the storage devices 1 and 32 often use general-purpose storage devices, whereas the instruction lengths of the processors 1 and 2 are arbitrary. The address depth of the internal memories 31 and 32 is usually 2
Since the program sizes of the processors 1 and 2 are arbitrary, the free areas 41 and 42 are almost always used.
An invalid area such as

Thereafter, the operation stop state of the processors 1 and 2 is released. The processor 1 reads the program from the address 0000 (hexadecimal notation) to the address 4000 (hexadecimal notation) from the internal memory 31 through the system bus 11, the bus arbitration circuit 5, and the system bus 21, and performs a normal operation. Similarly, the processor 2 communicates with the internal memory 3 via the system bus 12, the bus arbitration circuit 5, and the system bus 22.
2 and the normal operation is performed. At this time, the processors 1 and 2 can read the program in parallel. If the program size is larger than the capacity of the built-in memory 32, two methods are often used.

One is that when the program in the internal memory 32 reaches the last address ffff (hexadecimal notation) of the address, the bus arbitration circuit 5 causes the processor 2 to stop or wait, activates the controller 71, The remaining program is written by data transfer from the external memory 70 through the system buses 15, 16, and 22, for example, from the address 0000 (hexadecimal notation) of the internal memory 31. When the write is completed, the bus arbitration circuit returns the processor 2 to the normal operation state, and
A method generally called an overlay, which is performed from address 00 (hexadecimal notation), is used.

When the program before overwriting is executed again, data is transferred from the external memory 70 by the above-mentioned method, and the program is executed.

When such a method is used, it is not suitable for real-time processing called real-time processing, and it is necessary to provide a margin for processing time. In addition, if the access method is a simple access method called a real address space, the program itself needs to be devised, and the last address ffff (16
It is necessary to take measures such as adding a branch instruction from the address (in the base number) to the overwrite area of the program. In this conventional example, a branch instruction to the head address is added.

Second, program debugging requires a great deal of man-hours and attempts to compress the program size within the capacity of the built-in memory 32.

[0010]

In the conventional configuration of a memory device in which a plurality of processors and a readable and writable instruction memory corresponding to each processor are connected to one semiconductor chip, unevenness is caused in the free area of each memory device. On top of
When the shortage occurs, it is necessary to transfer the program data from the external memory.During this process, the processor is in a halt state, so there is a problem that real-time processing cannot be realized. Had the disadvantage of having to do so.

It is an object of the present invention to provide a memory device in which each processor can perform processing without impairing real-time processing in such a memory device and without adding special measures to a program.

[0012]

In order to solve this problem, a memory device according to the present invention has the following features. 1) A program of a processor having a shortage is stored in a memory device of another processor having a free area, and the program is stored in a memory in a backward direction. , The data is written in the reverse direction from the head to the head, or in the forward direction from the head to the end, and 2) an identification flag indicating the written memory device is provided.

[0013] Since the program of the processor, which is insufficient due to the above configuration, is in the free area of the memory device of the other processor, there is no need to stop the processor or wait and transfer data from the external memory. Capture and real-time processing are possible.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 shows a configuration of a memory device according to this embodiment.

In FIG. 1, 1 and 2 are processors, 5 is a bus arbitration circuit, 6 is an address converter, 11 and 12 are system buses connecting the processors 1 and 2 and the bus arbitration circuit 5, and 31 is a processor 1 A built-in memory in which programs are stored, 41 is a free area which is an invalid area in the built-in memory 31, 32 is a built-in memory in which programs of the processor 2 are stored, and 42 is a built-in memory 32
, An empty area which is an invalid area, and 20 is a system bus connecting the bus arbitration circuit 5 and the address converter 6,
A system bus 22 connects the address converter 6 and the built-in memories 31 and 32.

Reference numeral 70 denotes an external memory in which programs to be written in the internal memories 31 and 32 are stored in advance.
Reference numeral 71 denotes a controller for reading and writing to and from the external memory 70, 15 denotes a system bus connecting the external memory 70 and the controller 71, and 16 denotes a system bus connecting the controller 71 and the bus arbitration circuit 5. One semiconductor chip is constituted by components other than the external memory 70.

The operation of a memory device in which a plurality of processors and a readable / writable instruction memory corresponding to each processor are connected to one semiconductor chip configured as described above will be described below.

First, the processors 1 and 2 are set to a reset state or an operation stop state such as a halt state. The programs of the processors 1 and 2 are written in the external memory 70 in advance. This program is transferred to the built-in memory 31 through the system buses 15 and 16, the bus arbitration circuit 5, the system bus 20, the address converter 6 and the system bus 21 by using a high-speed data transfer function generally called a DMA transfer of the controller 71. Write to.

Similarly, the program is written into the internal memory 32 through the system bus 15, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22. Further, the shortage program of the processor 2 is written in the internal memory 31 from the address ffff (hexadecimal notation) address toward the head by the same means as described above.

Therefore, when the data transfer is completed, the program of the processor 1 stores 0000 (1) in the internal memory 31.
The program is written from address hex (hexadecimal notation) to address 4000 (hexadecimal notation).
The data is divided and stored at addresses up to ffff (hexadecimal notation) and from ffff (hexadecimal notation) in the internal memory 31 to fffc (hexadecimal notation). At this time, the free space 31 is smaller than that of the conventional example.

Thereafter, the operation stop state of the processors 1 and 2 is released. The processor 1 reads the program from the built-in memory 41 through the system bus 11, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 21, and performs a normal operation. Similarly, the processor 2 includes a system bus 12, a bus arbitration circuit 5, and a system bus 2
0, reads the program from the built-in memory 32 through the address converter 6 and the system bus 22, and performs a normal operation. At this time, the processors 1 and 2 can read the program in parallel.

When the processor 2 issues an address exceeding the capacity of the internal memory 32 after the program in the internal memory 32 reaches the last address ffff (hexadecimal notation) of the address in the processing of the processor 2, for example, 10000 When the address (in hexadecimal notation) is issued, the bus arbitration circuit 5 completes the reading of the processor 1 to the internal memory 31 and then reads the internal memory 31.

At this time, the issue address of the bus arbitration circuit 5 generates and reads out the one's complement ffff (hexadecimal notation) which is a bit inversion of the issue address 10000 (hexadecimal notation) of the processor 2 in the address converter 6.

Similarly, when the processor 2 issues the address 10001 (hexadecimal notation), the bus arbitration circuit 5 completes the reading of the processor 1 into the internal memory 31 and then the address converter 6 sends the address to the internal memory 31. A one's complement fffe (hexadecimal notation) which is a bit inversion is generated and read.

As described above, even a program exceeding the capacity of the built-in memory 32 can be processed in real time without suspending the operation of the processor 2, and the free space 41 of the built-in memory 31 can be effectively utilized.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. (Embodiment 2) FIG. 2 shows a configuration of a memory device according to the present embodiment.

The present embodiment has a configuration substantially similar to that of the first embodiment. However, the method of storing a part of the program of the processor 2 in the built-in memory 31 and the address conversion method of the address converter 6 are accordingly. different.

The operation of the memory device according to this embodiment will be described below. First, the processors 1 and 2 are set to a reset state or an operation stop state such as a halt state. The programs of the processors 1 and 2 are written in the external memory 70 in advance. This program is transferred to the built-in memory 31 through the system buses 15 and 16, the bus arbitration circuit 5, the system bus 20, the address converter 6 and the system bus 21 by using a high-speed data transfer function generally called a DMA transfer of the controller 71. Write to.

Similarly, the program is written in the internal memory 32 through the system bus 15, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22. In the internal memory 31, fffc in the middle of the empty area 41 is stored.
(Hexadecimal notation) From the address to the end of the address ffff
(Hexadecimal notation) The shortage program of the processor 2 is written toward the address direction by the same means as described above.

Therefore, when the data transfer is completed, the program of the processor 1 stores 0000 (1
The program is written from address hex (hexadecimal notation) to address 4000 (hexadecimal notation).
The addresses are divided into addresses up to the address ffff (hexadecimal notation) and from the address fffc (hexadecimal notation) of the internal memory 31 to the address ffff (hexadecimal notation). At this time, the free area 41 is smaller than that in the conventional example.

Thereafter, the operation stop state of the processors 1 and 2 is released. The processor 1 reads the program from the built-in memory 41 through the system bus 11, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 21, and performs a normal operation.

Similarly, the processor 2 is connected to the system bus 1
2. The program is read from the built-in memory 42 through the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22 to perform a normal operation. At this time, the processors 1 and 2 can read the program in parallel.

When the processor 2 issues an address exceeding the capacity of the internal memory 32 after the program of the internal memory 32 reaches the last address ffff (hexadecimal notation) of the address in the processing of the processor 2, for example, 10,000 When the address (in hexadecimal notation) is issued, the bus arbitration circuit 5 completes the reading of the processor 1 to the internal memory 31 and then reads the internal memory 31.

At this time, the issue address of the bus arbitration circuit 5 is obtained by subtracting 4 from the issue address 10000 (in hexadecimal notation) of the processor 2 in the address converter 6 and fffc.
(Hexadecimal notation) and read it out.

Similarly, when the processor 2 issues the address 10001 (in hexadecimal notation), the bus arbitration circuit 5 completes the reading of the processor 1 into the internal memory 31, and then the address converter 6 sends the address 4 to the internal memory 31. Is subtracted to generate ffffd (in hexadecimal notation) and read out.

As described above, even a program exceeding the capacity of the built-in memory 32 can be processed in real time without stopping the operation of the processor 2, and the free space 41 of the built-in memory 31 can be effectively utilized.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. (Embodiment 3) FIG. 3 shows a configuration of a memory device according to the present embodiment.

In FIG. 3, 1, 2 and 3 are processors,
5 is a bus arbitration circuit, 6 is an address converter, 11, 12,
13 is a system bus connecting the processors 1, 2, 3 and the bus arbitration circuit 5, 31 is a built-in memory for storing the program of the processor 1, 41 is a free space in the built-in memory 31 which is an invalid area, 51 Is an ID flag which is an identification flag of a memory for designating a reading destination when a program shortage occurs, 32 is a built-in memory in which a program of the processor 2 is stored, and 42 is a built-in memory 3
2, an empty area which is an invalid area, 52 is an ID flag which is an identification flag of a memory for designating a read destination when a program shortage occurs, 33 is an internal memory for storing a program of the processor 3, 43 Is a free area which is an invalid area in the internal memory 33, 20 is a system bus connecting the bus arbitration circuit 5 and the address converter 6,
21, 22 and 23 are an address converter 6 and a built-in memory 3.
1, 32 and 33 are system buses.

Reference numeral 70 denotes an external memory in which programs to be written in the internal memories 31, 32, and 33 are stored in advance, 71 denotes a controller that reads and writes data from and to the external memory 70, and 15 denotes an external memory and the controller 7.
1, a system bus connecting the controller 71 and the bus arbitration circuit 5; One semiconductor chip is constituted by components other than the external memory 70.

The operation of a memory device in which a plurality of processors and a readable / writable instruction memory corresponding to each processor are connected to one semiconductor chip configured as described above will be described below.

First, the processors 1, 2, 3 are put into a reset state or an operation stop state such as a halt state. The programs of the processors 1, 2, and 3 are written in the external memory 70 in advance. This program is transferred to the system buses 15 and 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, using a high-speed data transfer function generally called DMA transfer of the controller 71.
The data is written to the internal memory 31 through the system bus 21.

Similarly, the program is written to the internal memory 32 through the system bus 15, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22. Similarly, the program is stored in the internal memory 33 in the system bus 1.
5, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 23.

Further, the shortage program of the processor 2 is written in the built-in memory 31 from the address ffff (hexadecimal notation) address toward the head by the same means as described above. Therefore, when the data transfer is completed, the program of the processor 1 stores 0000 (1
The program is written from address hex (hexadecimal notation) to address 4000 (hexadecimal notation).
The data is divided and stored at addresses up to ffff (hexadecimal notation) and from ffff (hexadecimal notation) in the internal memory 31 to fffc (hexadecimal notation). At this time, the free area 41 is smaller than that in the conventional example.

At this time, an ID flag indicating the location of the continuation program is written into each program as supplementary information if the capacity exceeds the internal memory capacity. The IDs of the built-in memory 31 and the built-in memory 33 are “01” and “10”, respectively. ID “00” indicates that there is no continuation program.
In the ID flag 52, the continuation program is stored in the internal memory 31.
The flag “01” is written. Since there is no continuation program from addresses 0000 (hexadecimal notation) to 4000 (hexadecimal notation) of the internal memory 31, "00" is written in the ID flag 51. Since the continuation program from the address fffc (hexadecimal notation) to the address ffff (hexadecimal notation) of the internal memory 31 is the internal memory 33, the ID flag 51
Is written with "10".

Thereafter, the operation stop state of the processors 1 and 2 is released. The processor 1 reads the program from the built-in memory 31 through the system bus 11, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 21, and performs a normal operation.

Similarly, the processor 2 is connected to the system bus 1
2. The program is read from the built-in memory 32 through the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22 to perform a normal operation.

Similarly, the processor 3 is connected to the system bus 1
3. The program is read from the built-in memory 33 through the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 23 to perform a normal operation. At this time, the processors 1, 2, and 3 can read the program in parallel.

When the processor 2 issues an address exceeding the capacity of the internal memory 32 after the program of the internal memory 32 reaches the last address ffff (hexadecimal notation) of the address in the processing of the processor 2, for example, 10000 When the address (in hexadecimal notation) is issued, the bus arbitration circuit 5 sets the ID flag 52 of the previous access address to "0".
Since it is 1 ", the reading to the internal memory 31 of the processor 1 is completed and then the reading to the internal memory 31 is performed.

At this time, the 1-complement ffff (hexadecimal notation) which is a bit inversion of the issue address 10000 (hexadecimal notation) of the processor 2 is generated and read out from the address arbiter 5 by the address converter 6 in the address converter 6.

Similarly, when the processor 2 issues the address 10001 (in hexadecimal notation), the bus arbitration circuit 5 completes the reading of the processor 1 into the internal memory 31, and then the address converter 6 sends the address to the internal memory 31. A one's complement fffe (hexadecimal notation) which is a bit inversion is generated and read.

When the operation is continued in another memory,
In the same manner as above, reading can be performed as in a memory device having a continuous memory space.

As described above, even a program exceeding the capacity of the built-in memory 32 can be processed in real time without stopping the operation of the processor 2, and the free space 41 of the built-in memory 31 can be effectively used.

Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. (Embodiment 4) FIG. 4 shows a configuration of a memory device according to the present embodiment.

The present embodiment has a configuration substantially similar to that of the third embodiment. However, the method of storing a part of the program of the processor 2 in the built-in memory 31 and the address conversion method of the address translator 6 accordingly. different.

The operation of the memory device according to the present embodiment will be described below. First, the processors 1, 2, and 3 are put into a reset state or an operation stop state such as a halt state. The programs of the processors 1, 2, and 3 are written in the external memory 70 in advance. This program is transferred to the built-in memory 31 through the system buses 15 and 16, the bus arbitration circuit 5, the system bus 20, the address converter 6 and the system bus 21 by using a high-speed data transfer function generally called a DMA transfer of the controller 71. Write to.

Similarly, the program is written in the internal memory 32 through the system bus 15, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22. Similarly, the program is stored in the internal memory 33 in the system bus 1.
5, the controller 71, the system bus 16, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 23.

The built-in memory 31 has an empty area 41.
The missing program of the processor 2 is written by the same means as described above from the middle of the address fffc (hexadecimal notation) to the address ffff (hexadecimal notation).

Therefore, when the data transfer is completed, the program of the processor 1 stores 0000 (1) in the internal memory 31.
The program is written from address hex (hexadecimal notation) to address 4000 (hexadecimal notation).
The addresses are divided into addresses up to the address ffff (hexadecimal notation) and from the address fffc (hexadecimal notation) of the internal memory 31 to the address ffff (hexadecimal notation). At this time, the free area 41 is smaller than that in the conventional example.

At this time, if the information exceeds the capacity of the built-in memory in each program, an ID flag indicating the location of the continuation program is written. In the ID flag 52, a flag “01” indicating the built-in memory 31 is written in the continuation program. Address 0 of internal memory 31
Since there is no continuation program from addresses 000 (hexadecimal notation) to 4000 (hexadecimal notation), the ID flag 51
Is written with "00". From the address fffc (hexadecimal notation) to the address ffff (hexadecimal notation) of the built-in memory 31, “10” is written in the ID flag 51 because a continuation program exists in the built-in memory 33.

After that, the operation stop state of the processors 1 and 2 is released. The processor 1 reads the program from the built-in memory 41 through the system bus 11, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 21, and performs a normal operation.

Similarly, the processor 2 is connected to the system bus 1
2. The program is read from the built-in memory 42 through the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 22 to perform a normal operation. Similarly, the processor 3 reads the program from the built-in memory 43 through the system bus 13, the bus arbitration circuit 5, the system bus 20, the address converter 6, and the system bus 23 and performs a normal operation. At this time, the processors 1, 2, and 3 can read the program in parallel.

When the processor 2 issues an address exceeding the capacity of the built-in memory 32 after the program in the built-in memory 32 reaches the last address ffff (hexadecimal notation) of the address in the processing of the processor 2, for example, 10000 When the address (in hexadecimal notation) is issued, the bus arbitration circuit 5 sets the ID flag 52 of the previous access address to "1".
Since it is 0 ", reading from the processor 1 to the built-in memory 31 is completed, and then reading to the built-in memory 31 is performed.

At this time, the issue address of the bus arbitration circuit 5 is obtained by subtracting 4 from the issue address 10000 (in hexadecimal notation) of the processor 2 in the address converter 6 and fffc
(Hexadecimal notation) and read it out. Similarly, when the processor 2 issues the address 10001 (hexadecimal notation), the bus arbitration circuit 5 completes the reading of the processor 1 into the internal memory 31, and then the address converter 6 subtracts 4 from the address to the internal memory 31. fff
d (hexadecimal notation) is generated and read.

When continuing to another memory,
In the same manner, reading can be performed as in a memory device having a continuous memory space.

As described above, even a program exceeding the capacity of the built-in memory 32 can be processed in real time without stopping the processor 2, and the free space 41 of the built-in memory 31 can be effectively utilized.

[0067]

As described above, according to the present invention, even a program exceeding the capacity of the built-in memory can be processed in real time without stopping the processor.
Free space in other internal memory can also be used effectively.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a memory device according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a memory device according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram of a memory device according to a third embodiment of the present invention;

FIG. 4 is a configuration diagram of a memory device according to a fourth embodiment of the present invention;

FIG. 5 is a configuration diagram of a conventional memory device.

[Description of References] 1-3 Processor 5 Bus Arbitration Circuit 6 Address Converter 31-33 Internal Memory 41-43 Free Space 11-13, 15, 16, 20-23 System Bus 51,52 ID Flag 61,62 Activation Flag 70 External memory 71 Controller

Claims (3)

[Claims] A plurality of processors and a readable and writable instruction memory corresponding to each processor are connected to one semiconductor chip, and when an instruction capacity of one processor is insufficient, a program is stored in a free area of the instruction memory of another processor. A memory device for writing. 2. The program according to claim 1, wherein the program is written in the free area in the direction from the end to the head or in the middle of the free area in the direction from the end and read out in the writing direction.
A memory device as described. 3. An instruction flag is provided in the instruction memory, so that when an instruction capacity of one processor is insufficient, a program is fetched from a free area of the instruction memory of another processor according to information written in the identification flag. The memory device according to claim 1 or 2, wherein: