JPS63186358A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data while extending an address with and to reduce the transfer loss by providing an address counter to the controller of a local memory to convert the data size of the memory. CONSTITUTION:A main memory 2 having the 32-bit data width, the CPU 4 of the 8-bit data width, and a terminal equipment 3 containing local memories 5A and 5B are connected to a system bus 1 having the 32-bit data width. A memory controller 6 of the equipment 3 contains as address counter which converts the data size and controls the area accesses of both memories 5A and 5B. When data are transferred to the memory 2 from the memories 5A and 5B, the base address of the memory 2 is set at a system bus 7 to carry out an area access. Thus data are transferred to the memory 2 while the 8-bit width is automatically extended to the 32-bit width. Thus the data transfer loss is reduced.

Description

TECHNICAL FIELD The present invention relates to a data transfer method, and more particularly to a data transfer method that is effective when transferring data between memories having different bus widths.

Conventional technology In the past, when data was transferred between memories with different bus widths, the transfer was usually performed according to the narrower bus width, which caused the efficiency of the wider bus to deteriorate. There was a problem.

Additionally, in order to solve the above problem, it may be possible to latch data according to the wider bus width, but in this case, another problem arises in that it takes time to latch. .

Purpose The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional data transfer methods and to provide a data transfer method that reduces loss during transfer. It is about providing.

Configuration The above object of the present invention is to provide a system in which a local memory having a data width different from that of the memory is connected to a computer system having a memory connected to a system bus. This is achieved by a data transfer method characterized by providing an address counter for converting to the data size of the bus and performing data transfer while expanding the address width.

Hereinafter, the configuration of the present invention will be explained in more detail based on examples. In the following explanation, an example will be exemplified in which an 8-bit CPU having a local memory transfers data to and from a memory on a 32-bit data width bus.

FIG. 1 is a block diagram of an example of a system configuration showing an embodiment of the present invention. In the figure, 1 is a system bus having a data width of 32 pins, 2 is a main memory which also has a data width of 32 bits, and 3 is a CPU 4 . It also shows a terminal device having a plurality of local memories 5A, 5B, . . . having a data width of 8 bits.

Note that 6 in the terminal device 3 represents a memory control, which will be described later, and 7 represents an interface with the system bus 1 (hereinafter referred to as "system bus I/FJ").

In the above system, the main memory 2 having a data width of 1.32 bits is connected to the system bus 1, and the main memory 2, which also has a data width of 8 bits, is connected to the system bus 1 via the CPU 4 and the memory control 6, which have a data width of 8 bits. A plurality of local memories 5A, 5B, . . . are connected to the system bus 1 through a system bus I/F 7.

Each of the local memories 5A, 5B, . . . can be accessed with the following two data widths. That is, C.P.
U4 has a data width of 8 bits, and also has a data width of 8 bits.
can be accessed with a data width of 32 bits.

Here, the local memories 5A, 5B, . . . are mapped to the CPU 4 as shown in FIG. 2, and access to the areas 8, 9, 10 is controlled from the memory controller 6.

FIG. 2 shows the relationship between the real addresses (physical addresses) of each of the local memories 5A, 5B, . The memory control 6 has an address counter, and each local memory 5A, 5B
, . . . Controls access to areas 8, 9, and 10.

The address output from C and PO2 is counted up by the address counter in the memory control 6 as follows depending on the area to be accessed.

Namely.

(1) When accessing area 8 +1 count up.

This corresponds to the case where the CPU 4 normally accesses the local memories 5A, 5B, .

(2) When accessing areas 9 and 10, the count increases by +4.

System bus 1 and local memories 5A and 5B.

...corresponds to which data transfer is to be performed.

The system bus I/F 7 receives an address signal (ADRO) and a control signal (CNT) output from the CPU 4.
LO), the system bus address signal (ADR
) and a control signal (CNTL). Also,
The system bus I/F 7 has a built-in register (not shown) for storing a base address for transfer to the system bus 1, and when accessing the areas 9 and 10, the contents of the base address storage register and the CPU 4 The address value output from system bus 1 is added to
is output to.

In addition, the control signal of the system bus 1 (CNT
L) is of first order.

(1) READ to area 9, WRITE to area 10, WRITE to memory 2 (2) WRITE to area 9, READ to area 10, READ from memory 2 Therefore, the local memories 5A, 5B, etc. When transferring data from to memory 2, use the system bus I/F
When the base address of memory 2 is set in the base address storage register of area 7 and a block transfer instruction or DMA from area 9 to area 0 is executed, automatically
Sequential memory 2 while expanding the bit width to 32 bits
A block transfer is performed. Furthermore, when data is transferred from the memory 2 to the local memories 5A, 5B, . . . , data may be transferred to the area 9 or 10 in the same manner.

That is, the above region 9. In the transfer with IO, no transfer is actually performed during this time, and the timing for outputting to the system bus 1 is created using only the timing of the output from the CPU 4.

FIG. 3 is a diagram showing a specific example of the configuration of the terminal device 3. As shown in FIG. In the figure, TR is a transceiver, LM is an 8-byte local memory, AC is a local memory address counter, and CTLR is a chip select, R/W signal, and bus direction control generation circuit. These constitute the controller 6.

Furthermore, if the area 9 is further divided into two areas 9A and 9B and the data flow is controlled as follows by access by the CPU 4, more efficient data transfer can be performed.

(1) When CPU 4 reads area 9A, the direction of data is from system bus 1 to local memory. (2) When CPU 4 places area 9B in WRI, the direction of data is from system bus 1 to local memory. (3) Area When the CPU 4 writes the area 9A, the data direction is from the local memory to the system bus 1. (4) When the CPU 4 reads the area 9B, the data direction is from the local memory to the system bus 1. This is shown as one example, and it goes without saying that the present invention should not be limited to this.

Effects As described above, according to the present invention, the device is connected to the system bus. In a system in which a local memory having a data width different from the memory is connected to a computer system having a memory, the controller of the local memory is provided with an address counter for converting data in the local memory to a data size of a system bus, Since data transfer is performed while expanding the address width, it is possible to realize a data transfer method that reduces loss during transfer, which is a remarkable effect.

Further, in a system in which a local memory having a data width different from that of the memory and a local CPU are connected to a computer system having a memory connected to a system bus, a memory control means having a bus control signal conversion circuit is provided to By controlling the CPU to perform two READ or two WRITE operations with one transfer command, the transfer efficiency can be significantly improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a system configuration example showing an embodiment of the present invention, FIG. 2 is a diagram showing a mapping situation of a local memory to a local CPU, and FIG. 3 is a block diagram of a system configuration example showing an embodiment of the present invention.
! It is a figure which shows the specific example of a structure of t3. 1 system bus, 2: main memory, 3: local C
PU, 5A, 5B, ... and LM: Local memory, 6: Memory control, 7: System bus I/F
, TR: Transceiver, AC: Local memory address counter.

Claims (3)

[Claims] (1) In a system in which a local memory having a data width different from that of the memory is connected to a computer system having a memory connected to a system bus, the controller of the local memory converts the data of the local memory to the data size of the system bus. A data transfer method that is characterized by providing an address counter for data transfer and performing data transfer while expanding the address width. (2) In a computer system having a memory connected to a system bus, in which a local memory having a data width different from that of the memory and a local CPU are connected, a memory control means having a bus control signal conversion circuit is provided to A data transfer method characterized by controlling such that READ is performed twice or WRITE is performed twice with one transfer command from the CPU side. (3) The data transfer method according to claim 2, wherein an address output by the local CPU is used to generate a system bus address.