JPH0537312Y2 - - Google Patents

Description

[Detailed Description of the Invention] "Field of Industrial Application" The present invention relates to a direct memory access control device installed in a computer system, and is particularly intended to improve functionality during access.

``Prior art'' A direct memory access control device including a microprocessor installed in a computer system.
A controller (hereinafter referred to as DMAC) is an LSI that has a function of transferring data at high speed between a memory and an input/output unit or between memories.

This DMAC has a function of outputting a memory address of a data transfer destination and a function of controlling control signal lines for the memory, input/output section, etc.

Additionally, this LSI-based DMAC usually has an address width of 23 bits (A23 to A1), and this DMAC can be used in computer systems that exceed this address width, for example, with an address width of 31 bits (A31 to A1).
When applying DMAC, a device as shown in FIG. 3 is configured.

In other words, the microprocessor μP1 is a 31-bit processor.
Address bus AB, 16-bit data bus
It has a DB and controls data transfer between, for example, the memory 3 and the input/output unit 4 via the DMAC 2.

At this time, DMAC2 has an address width of MAR<
7:1>, MAR<15:8>, MAR<23:16>
To compensate for this, an 8-bit expansion memory address register 5 (extension register 5, MAR<31:24>) is externally connected to the address bus AB.

When DMA is activated in such a system, DMAC2 sends out a 23-bit address in accordance with the 31-bit direct memory access designation address generated from microprocessor μP1.
Extension register 5 sends out an 8-bit address
Constructs a 31-bit address and performs DMA operations.

``Problem that the invention attempts to solve'' In the above system, the contents of the extension register 5 are always fixed, and the contents of the upper 8 bits MAR<31:24> cannot be updated during DMA transfer. However, the drawback was that DMA transfer of memory areas whose addresses exceeded the 24-bit boundary was not possible.

That is, if the DMA specified address is, for example, #
From address 00FFFF00 to address #010001FF,
Since the upper 8-bit address is fixed to “00” in extension register 5, the upper digits “00” to “01”
update was no longer possible, and DMA transfers specifying such addresses were no longer possible.

This invention solves the above-mentioned problem, and it always
The purpose is to realize a direct memory access control device that can perform DMA transfer.

``Means for solving the problem'' The present invention that solves the above problems changes the contents of the expansion register,
Its specific configuration is as follows.

That is, a direct memory access control system in which a microprocessor and a direct memory access controller, which has an address width smaller than the system address width and controls data transfer, are connected by an address bus and a data bus. In the device, the direct memory access transfer is performed during the direct memory access transfer.
An extension register in which the upper address bits added to the upper side of the address width of the controller are set, and an extension register in which the upper address bits added to the upper side of the address width of the controller are set, and
It is detected that the address width boundary of the access controller is exceeded, and the internal address of the direct memory access controller is
a control circuit that increments a counter; and an arithmetic unit that takes in a value in the extension register, increments it by +1, and transfers the value to the extension register based on a signal that the control circuit detects that the address width has reached a boundary. This is a direct memory access control circuit characterized in that it is provided with a.

"Operation" In the direct memory access control device of the present invention, when a DMA address exceeds the boundary of a predetermined address width during a DMA transfer operation, the arithmetic unit increments the contents of the extension register by 1, The value of and direct memory access
Combines the address bits of the controller, sends the address, and performs DMA access.

Embodiment FIG. 1 is a block diagram showing the configuration of a direct memory access control device embodying the present invention.

In this figure, 1 and 2 are microprocessors μP and 2, respectively, which are the same as the conventional device shown in FIG.
direct memory access controller
It is DMAC.

6 is the upper 8 bits of the address (MAR<
31:24>) Extension register 7 takes in the output (A31 to A24) of extension register 6 and inputs it to +
an incrementing arithmetic unit that outputs a value of 1;
8 is an initial value buffer that sets an initial value in the expansion register 6 according to the specification of the microprocessor μP1;
Reference numeral 9 denotes a control circuit that controls the expansion register 6, the arithmetic unit 7, and the initial value buffer 8.

When the microprocessor μP1 sets an initial value in the extension register 6, the control circuit 9 enables the output of the initial value buffer 8 and makes the write clock CLK of the extension register 6 active. Furthermore, when it is detected that the memory address for DMA transfer exceeds the 24-bit boundary, it is necessary to update the contents of the extension register 6, so the output of the arithmetic unit 7 is enabled and the write clock CLK is applied to the extension register 6.

The direct communication system of the present invention configured as described above
The operation of the memory access control device will be explained in detail using the flowchart of FIG.

First, μP1 connects DMAC2 with MAR<23:1
> (address 23 bits) and other parameters. At the same time, μP1 sets upper address bits MAR<31:24> (8 bits) to initial value buffer 8. Furthermore, this initial value is
is set in the extension register 6 at the write timing.

Then, DMAC2 is the address MAR<23:1> set in the internal register and extension register 8.
DMA is activated by address MAR<31:24>.

During DMA transfer, the DMAC 2 sends out the address MAR<23:1> and the extension register 6 sends out the upper address MAR<31:24> for each word transfer.

The DMAC 2 itself determines whether the DMA transfer is completed using an internal counter of the DMAC 2.

The control circuit 9 always sends an address on a 24-bit boundary (A23 to A1 are all 1).
If it is a 24-bit boundary, the internal address of DMAC2 is determined by hardware.
The counter and arithmetic unit 7 are incremented. Then, at the next timing, the output of the arithmetic unit 7 is given to the extension register 6, and the contents of the extension register 6 are +
Incremented by 1. By using the sending address of the extension register 6 and the sending address from the DMAC 2, it is possible to send an address across the 24-bit boundary, and DMA transfer can be continued.

On the other hand, if the address being sent does not reach the 24-bit boundary, the DMAC 2 increments only the internal address counter and continues the DMA transfer.

As mentioned above, the direct memory of this invention
The access control device is sent from DMAC223
By updating the contents of the extension register 6, DMA operations can be performed not only on bit addresses but also on addresses that exceed 24-bit boundaries.

``Effect of the invention'' In the direct memory access control device of the invention, during a DMA transfer operation, when a DMA address exceeds a predetermined address width, the arithmetic unit increments the contents of the extension register by 1, and DMA access is performed by combining the value of the address bit of the direct memory access controller and sending the address, so DMA transfer can always be executed smoothly without being aware of the value of the DMA specified address. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a direct memory access control device implementing the present invention, Fig. 2 is a flowchart showing the operation of the device of the present invention, and Fig. 3 is a conventional direct memory access control device. FIG. 1... Microprocessor μP, 2... Direct memory access controller DMAC,
3... Memory, 4... Input/output unit, 5, 6... Extension register, 7... Arithmetic unit, 8... Initial value buffer, 9... Control circuit.

Claims (1)

[Scope of utility model registration request] In a direct memory access control device in which a microprocessor and a direct memory access controller having an address width smaller than the system address width and controlling data transfer are connected by an address bus and a data bus. , an extension register in which upper address bits added to the upper side of the address width of the direct memory access controller are set during a direct memory access transfer; detects that the address in the direct memory access controller exceeds the address width boundary of the direct memory access controller;
A control circuit that increments an internal address counter of the access controller, and a signal that detects that the address width has reached a boundary in the control circuit, takes in the value in the expansion register, increments it by +1, and transfers the value to the expansion register. A direct memory access control circuit characterized by being provided with an arithmetic unit that transfers data to a register.