JPH04112222A - Semiconductor file memory device - Google Patents

Abstract

PURPOSE:To transfer data at a high speed by accessing a memory array with the address obtained by adding the start address of a page held in a latch circuit and the relative address outputted from a relative address generating circuit. CONSTITUTION:This device consists of an interface 3 for data transmission and reception between a memory array 4 and an external computer 9 and a control part 5 which performs the read/write processing for the memory array 4, and the control part 5 consists of a processor 2, a latch circuit 10, a relative address generating circuit 11, and an adding circuit 12. Since the memory array is accessed with the address obtained by adding the address held in the latch circuit 10 and the address outputted from the relative address generating circuit 11, it is unnecessary to perform the page switching processing at the time of the change of the page during read/write processing, Thus, data is transferred at a high speed though the address space of the memory array 4 is larger than the address space which an MPU can directly address.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor file memory device, and more specifically, a semiconductor file memory device with an improved addressing method in data read or write processing (read/write processing). Regarding.

[Prior Art] Currently, as an alternative to magnetic disk devices, semiconductor file memory devices using semiconductor memories as storage elements are being put into practical use as external storage devices for computers and the like. A semiconductor file memory device includes a memory array,
It consists of a microprocessor (MPU) that performs read/write processing to the memory array, an interface that exchanges data with an external computer, and the like.

In conventional semiconductor file memory devices, if the address space of the memory array is larger than the address space that can be directly addressed by the MPU, a part of the address space that can be directly addressed by the MPU is allocated for accessing the memory array. , the address space of the memory array is divided into pages, each of which is defined as one page, and each page is accessed by an external computer to perform read/write processing on each page. Also, M
Similar read/write processing is performed when a DMA controller is used instead of the PU.

[Problems to be Solved] However, such conventional semiconductor file memory devices have the following problems.

Since the MPU or DMA controller performs read/write processing to the memory array on a page-by-page basis, page switching processing is required when the processing spans multiple pages.

Therefore, in a memory array, read/infiltration processing must be temporarily suspended to perform page switching processing even if the address is a series of -. This increases MPU processing and slows down the data transfer speed. Become.

The present invention is intended to solve these conventional problems, and aims to provide a semiconductor file memory device that does not require processing when switching pages and can transfer data at high speed.

[Means for Solving the Problems] In order to achieve this object, the semiconductor file memory device of the present invention is characterized in that a control circuit controls a processor and a designated read 7m output from the processor to start the read process. a latch circuit that holds the start address of the specified page; and a latch circuit that receives from the processor the address of the difference between the address at which read/write processing for the specified page is started and the start address of that page and outputs it at the start of data transfer; Thereafter, there is a relative address generation circuit that increments or decrements and outputs the difference address every time a read/write process is performed, and receives the output of the latch circuit and the output of the relative address generation circuit, and adds the value to the memory array. and an adder circuit that outputs the output to the address terminal of the address terminal.

[Operation] Since the memory array is accessed using the at trace obtained by adding the address held in the latch circuit and the address output by the relative address generation circuit, page switching processing is performed when the page changes during read/write processing. There is no need to do this. As a result, there is no interruption of read/write processing during data transfer, and high-speed data transfer can be performed even when the address space of the memory array is larger than the address space that the MPU can directly address. It becomes possible.

[Example 1] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a principle diagram of an embodiment of a semiconductor file memory device to which the present invention is applied.

In the same figure, a semiconductor file memory device 1 includes an interface 3 that exchanges data between a memory array 4 and an external computer 9, and a control unit 5 that performs read/write processing for the memory array 4. In addition, the control unit 5 includes a processor 2, a latch circuit 1
0, a relative address generation circuit 11, and an addition circuit 12. These are connected by data bus 6, address bus 7, buses 13, 14, 15 and control signal lines 8 as shown in the figure.

FIG. 2 is a block diagram of a circuit example embodying the principle diagram shown in FIG. 1.

In the figure, a processor 2 includes an MPU 21 and a decoder 2.
2, and the decoder 22 has an interface 3. Latch circuit 10. Alternatively, a chip select signal for selecting any device in the relative address generation circuit 11 is output. Note that, as the interface 3, the SC8I controller 31 is used here as an example. The latch circuit 10 is
In order to hold the start address of an externally specified page sent from the MPU 21, it is composed of as many D flip-flops as necessary. The relative address generation circuit 11 is composed of a DMA controller 111 and an address connection switching circuit 112. The address connection switching circuit 112 connects the address to be accessed and the latch circuit 10.
When outputting the address (hereinafter referred to as relative address) that is the difference from the top address of the page held in the DMA controller 111 to the adder circuit 12, the signal transmission is blocked so that the output does not affect other devices. It is something. The addition circuit 12 includes the same number of adders 121 as the number of bits required to access the memory array 4.

When data is transferred between the memory array 4 and the external computer 9, the MPU 21 first transfers data to the latch circuit 10.
Sends a signal to the decoder 22 to select the
sends 1000 knob select (number 3) to the latch circuit. At this time, the MPU 21 outputs the start address of the page via the data bus 6 to the latch circuit 10 based on the page specified from the outside, and 10 holds its output.

Next, the MPU 21 sends a signal for selecting the DMA controller 111 to the decoder 22. As a result, the decoder 22 transfers the chip select signal to the DMA controller 11.
Send to 1. At this time, based on the start address, end page, and end address specified from the outside, the MPU 21
writes the relative address (corresponding to the start address position) and the number of transfer data (corresponding to the end address position) to the DMA controller 111, and causes the DMA controller to transfer the data.

When the DMA controller 111 receives control from the MPU 21, it stops the operation of the MPU 21.

Thereafter, the DMA controller 111 outputs the relative address to the adder circuit 12. The adder circuit 12 is the launch circuit 1
The start address of the page output from 0 and the relative address output from the DMA controller 111 are added to create a start address to be accessed, and output to the address terminal of the memory array 4 via the bus 15. At this time D
The MA controller 111 is the scs i controller 31
Read or write control signals (RD, WR) and REQ from
(DMA request signal), and controls data transfer between memory array 4 and external computer 9 accordingly.

The DMA controller 111 is the SC8I controller 3
When receiving the REQ signal from the MPU 1 and the relative address and number of transferred data from the MPU 21, it outputs HALT to stop the MPU 21), and sends the AC to the 5C8I controller 31.
A K signal is output to directly connect the memory array 4 and the SC8I controller 31, so that one side is read and the other is written. Then, each time a read/write process is performed, the relative address is incremented or decremented and this process is repeated. When the transfer process for the designated number of transfer data is completed, the DMA controller transfers control to the MPU 21, returns the address connection switching circuit 112 to its original state, and terminates the data transfer.

As explained above, interface 3 is 5C8I
Although a controller is used as an example, it is of course possible to use other types of interfaces.

The memory array may also be removable from the semiconductor file memory device.

[Effects of the Invention] As can be understood from the above explanation, the present invention has the following effects:
・The memory array is accessed using the address obtained by adding the top address of the page held in the 7-chi circuit and the relative address output by the relative address generation circuit, so even if data transfer spans multiple pages, the relative address will not be used. Transfer processing can be performed continuously by incrementing or decrementing . As a result, when the page during read/write processing changes, the read/write processing is not interrupted to perform page switching processing, and high-speed data transfer is possible.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of an embodiment of a semiconductor file memory device to which the present invention is applied, and FIG. 2 is a block diagram of a circuit example embodying the principle diagram shown in FIG. DESCRIPTION OF SYMBOLS 1...Semiconductor file memory device, 2...Processor, 3...Interface, 4...
・Memory array, 5...control unit, 6...data bus, 7...address bus, 8...control all signal line,
9... Computer, 10... Latch circuit, 10.
... Relative address creation circuit, 12 ... Addition circuit, 13
．． 14.15...Bus, 21...MPU. 22... Decoder, 31... SC3I controller, 101... D flip-flop, 111... DMA controller, 112... Address switching circuit, 121... Adder.

Claims (3)

[Claims] (1) A memory array composed of semiconductor memory, a control circuit that performs read or write processing to this memory array, and an external device that specifies and accesses a page and exchanges data with this external device. the control circuit has a processor;
A latch circuit that holds the start address of the specified page outputted from this processor to start the read or write process, and a latch circuit that holds the start address of the specified page for starting the read or write process in the page and the difference between the start address of the page and the start address of the page. a relative address generation circuit that receives an address from the processor, outputs the difference address at the start of data transfer, and then increments or decrements and outputs the difference address each time the read or write process is performed; and the latch. A semiconductor file memory device comprising: an adder circuit that receives the output of the circuit and the output of the relative address generation circuit, and outputs a value obtained by adding the two to an address terminal of the memory array. (2) The semiconductor file memory device according to claim 1, characterized in that a DMA controller is used in the relative address generation circuit. (3) The semiconductor file memory device according to claim 1, wherein the memory array is removable.