JPH02111842U - - Google Patents
Info
- Publication number
- JPH02111842U JPH02111842U JP1880689U JP1880689U JPH02111842U JP H02111842 U JPH02111842 U JP H02111842U JP 1880689 U JP1880689 U JP 1880689U JP 1880689 U JP1880689 U JP 1880689U JP H02111842 U JPH02111842 U JP H02111842U
- Authority
- JP
- Japan
- Prior art keywords
- data buffer
- dma transfer
- scsi
- data
- perform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Bus Control (AREA)
Description
第１図は本考案に係るＳＣＳＩインターフエイ
ス回路の一実施例を示す要部構成図、第２図は本
考案のＳＣＳＩインターフエイス回路を用いたシ
ステムの構成図、第３図および第４図は動作フロ
ーを示す図、第５図はデータバツフアの構成を示
す図、第６図は従来のＳＣＳＩインターフエイス
回路を用いたシステムの構成図、第７図はチヤネ
ルバス専有時間について説明するための図である
。
２１…ＣＰＵ、２２…ＤＭＡ制御部、２３…チ
ヤネルバス制御部、２４…データバツフア、２５
…ＳＣＳＩバス制御部、２６…アドレスバス、２
７…データバス。
FIG. 1 is a block diagram of main parts showing an embodiment of the SCSI interface circuit according to the present invention, FIG. 2 is a block diagram of a system using the SCSI interface circuit of the present invention, and FIGS. 3 and 4 are Figure 5 is a diagram showing the operation flow, Figure 5 is a diagram showing the configuration of a data buffer, Figure 6 is a diagram showing the configuration of a system using a conventional SCSI interface circuit, and Figure 7 is a diagram explaining the channel bus exclusive time. . 21... CPU, 22... DMA control unit, 23... Channel bus control unit, 24... Data buffer, 25
...SCSI bus control unit, 26...Address bus, 2
7...Data bus.
Claims (1)
タにＳＣＳＩプロトロルをサポートするデバイス
を接続するＳＣＳＩインターフエイス回路におい
て、 ＤＭＡ転送用のデータバツフアと、 前記ホストコンピユータの主記憶装置とＳＣＳ
Ｉデバイス間のＤＭＡ転送を行なう際、ＳＣＳＩ
デバイスへ書き込むときは最初に主記憶装置から
データバツフアへのＤＭＡ転送を行いすべてのデ
ータがデータバツフアに格納された後データバツ
フアからＳＣＳＩデバイスへのＤＭＡ転送を実行
し、デバイスから読み出すときは最初にデバイス
からデータバツフアへのＤＭＡを行いすべてのデ
ータがデータバツフアに格納された後データバツ
フアから主記憶装置へのＤＭＡ転送を実行する機
能を有する手段 を具備したことを特徴とするＳＣＳＩインター
フエイス回路。[Claim for Utility Model Registration] In a SCSI interface circuit that connects a device that supports the SCSI protocol to a host computer that does not have a DMA restart function, a data buffer for DMA transfer, a main storage device of the host computer, and an SCS
When performing DMA transfer between I-devices, SCSI
When writing to a device, first perform a DMA transfer from the main memory to the data buffer, and after all data is stored in the data buffer, perform a DMA transfer from the data buffer to the SCSI device. When reading from the device, first perform a DMA transfer from the device to the data buffer. 1. A SCSI interface circuit comprising means for performing DMA transfer from the data buffer to a main storage device after all data is stored in the data buffer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1880689U JPH02111842U (en) | 1989-02-20 | 1989-02-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1880689U JPH02111842U (en) | 1989-02-20 | 1989-02-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02111842U true JPH02111842U (en) | 1990-09-06 |
Family
ID=31233774
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1880689U Pending JPH02111842U (en) | 1989-02-20 | 1989-02-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02111842U (en) |
-
1989
- 1989-02-20 JP JP1880689U patent/JPH02111842U/ja active Pending
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