JPH026340U - - Google Patents

Info

Publication number
JPH026340U
JPH026340U JP8401488U JP8401488U JPH026340U JP H026340 U JPH026340 U JP H026340U JP 8401488 U JP8401488 U JP 8401488U JP 8401488 U JP8401488 U JP 8401488U JP H026340 U JPH026340 U JP H026340U
Authority
JP
Japan
Prior art keywords
signal
supplied
control signal
buffer circuit
floating state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8401488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8401488U priority Critical patent/JPH026340U/ja
Publication of JPH026340U publication Critical patent/JPH026340U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図で
ある。 1……内部CPU、2……アドレスバス信号、
3……データバス信号、4……メモリ制御信号、
5,6,7……バツフア回路、8,9……電気的
書換可能ROM、10……メモリ用アドレス信号
、11……メモリ用データ信号、12……メモリ
用制御信号、13……バツフア回路制御信号、1
4……外部接続機構。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1...Internal CPU, 2...Address bus signal,
3...Data bus signal, 4...Memory control signal,
5, 6, 7...Buffer circuit, 8, 9...Electrically rewritable ROM, 10...Memory address signal, 11...Memory data signal, 12...Memory control signal, 13...Buffer circuit control signal, 1
4...External connection mechanism.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 内部CPUと、前記内部CPUからアドレスバ
ス信号、データバス信号およびメモリ制御信号が
供給されバツフア回路制御信号が供給されたとき
に出力がフローテイング状態になる複数のバツフ
ア回路と、フアームウエアを格納した電気的書換
可能ROMと、前記バツフア回路がフローテイン
グ状態になつているときに外部に接続されたRO
M書込装置からの信号を前記電気的書込可能RO
Mへ供給するための外部接続機構とを含むことを
特徴とする情報処理装置。
An internal CPU, a plurality of buffer circuits whose outputs are in a floating state when an address bus signal, a data bus signal, and a memory control signal are supplied from the internal CPU and a buffer circuit control signal is supplied, and firmware are stored therein. an electrically rewritable ROM and an RO connected to the outside when the buffer circuit is in a floating state;
The signal from the M writing device is transferred to the electrically writable RO.
An information processing device comprising: an external connection mechanism for supplying data to M.
JP8401488U 1988-06-24 1988-06-24 Pending JPH026340U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8401488U JPH026340U (en) 1988-06-24 1988-06-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8401488U JPH026340U (en) 1988-06-24 1988-06-24

Publications (1)

Publication Number Publication Date
JPH026340U true JPH026340U (en) 1990-01-17

Family

ID=31308714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8401488U Pending JPH026340U (en) 1988-06-24 1988-06-24

Country Status (1)

Country Link
JP (1) JPH026340U (en)

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