JPH02310749A - Cache main memory control system - Google Patents

Abstract

PURPOSE:To enable data hit on a cache to be read out with a processor during performing the write of the data on a main memory by providing a bidirectional data buffer for the main memory. CONSTITUTION:When a write operation by the processor 5 is performed, write data outputted to a data bus 6 is held in a shared data buffer 4, and next, the data is transferred to a data buffer 3. At this time, when the write operation is hit on the cache 1, the write operation is performed on the cache 1 simultaneously. And the write operation on the main memory 2 is performed based on the data held at the data buffer 3, and the data read out by hitting the cache 1 is read in the processor 5 via the shared data buffer 4. Thereby, the data hit on the cache can be read out without depending on whether or not the write operation on the main memory 1 from the data buffer 3 is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache/main memory control system for small-sized information processing devices and the like.

[Conventional technology]

Conventionally, in this type of control system, only a bidirectional data buffer shared between the cache and main memory existed between the processor and the cache and main memory.

[Problem to be solved by the invention]

In the conventional cache/main memory control method described above, the data buffer is shared between the cache and the main memory, so when writing data, the time required for writing depends on the access time of the main memory. When the processor reads data after an operation, even the data that hit the cache cannot be read until the write to the main memory is finished, so the processor is forced to wait, making it impossible to effectively utilize the performance of the cache. There were drawbacks.

[Means to solve the problem]

The configuration of the cache/main memory control method of the present invention is as follows:
In a control method for a cache and main memory of a small information processing device, etc., a first bidirectional data buffer shared with the main memory is provided between the processor and the cache, and the first bidirectional data buffer is A second bidirectional data buffer is further provided between the buffer and the main memory, allowing the processor to read hit data from the cache during an operation of writing data from the processor to the main memory. It is characterized by

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a main block diagram of a cache/main memory control system according to an embodiment of the present invention, in which a cache 1, main memory 2, data buffer 3, shared data buffer 4
, a processor, and a data bus 6.

FIG. 2 is a timing chart in this embodiment,
The operation will be explained below with reference to FIGS. 1 and 2.

When the processor 5 performs a write operation, write data is output onto the data bus 6. After holding the write data in the shared data buffer 4, the processor 5 ends the write operation. Next, the data held in the shared data buffer 4 is transferred to the data buffer 3.

At this time, if the write operation hits the cache, the data is transferred from the shared data buffer 4 to the data buffer 3, and at the same time, the write operation is also performed on the cache. When the write operation to the cache and the transfer operation to the data buffer 3 are completed, the shared data buffer 4 stops holding the write data.

A write operation to main memory 2 is performed using data buffer 3.
Based on data held in .

Furthermore, from the perspective of the processor 5, the write operation is completed once the data is held in the shared data buffer 4, so the read operation is started. At this time, the shared data buffer 4
Since the above operation has already been completed, the data is released, and the data hit and read from the cache is read into the processor 5 via the shared data buffer 4 and the data bus 6.

That is, it becomes possible to read data that has been hit into the cache, regardless of whether the write operation from the data buffer 3 to the main memory has been completed.

〔Effect of the invention〕

As explained above, by newly adding a second bidirectional data buffer for the main memory, the processor can read data hit in the cache while writing data to the main memory. effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main block diagram showing a cache/main memory control system according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of this embodiment.

1...cache, 2...main memory, 3...
Data buffer, 4... Cache/main memory shared data buffer, 5... Processor, 6... Data bus.

Claims (1)

[Claims] In a control method for a cache and main memory of a small information processing device, etc., a first bidirectional data buffer shared with the main memory is provided between the processor and the cache, and the first bidirectional data buffer is A second bidirectional data buffer is further provided between the buffer and the main memory, allowing the processor to read hit data from the cache during an operation of writing data from the processor to the main memory. A cache/main memory control method that is characterized by: