JP3171289B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus comprising a plurality of processors sharing a main memory and erasing the contents of an address translation buffer for implementing a virtual memory.

[0002]

2. Description of the Related Art JP-A-59-107477 discloses that
A conventional technique of this kind is disclosed. The system described in this publication includes a plurality of CPUs 1 and 2,
Main storage controller (hereinafter SCU) 1 connected to
The SCU 100 includes an address translation buffer (hereinafter, TLB) 3 and an address array (hereinafter, AA). In this system, a certain CPU 1
When the address translation is required by referring to the TLB3 from the above, the address translation process is performed. During this address conversion, an access request from another CPU 2 to the SCU 100 can be accepted. If the desired translation pair does not exist in the TLB 3 in this access request, the access request must be redone from the beginning after the address translation by the preceding access request.

[0003]

In the conventional system,
Since the access is permitted during the address translation process by the preceding access request, if the desired translation pair does not exist in the TLB, the access request must be redone from the beginning, resulting in a waste of time. was there.

[0004]

An information processing apparatus according to the present invention analyzes an instruction, outputs an erasure instruction signal when the instruction is a translation information erasure instruction of an address translation buffer, and involves reading / writing of a main memory. Instruction analysis means (hereinafter, instruction analysis unit) for outputting a logical address of main memory when the instruction is an instruction;
Erasing means (hereinafter referred to as "erasing means") which erases information about the logical address designated by the erase instruction signal from the instruction analysis unit from the address translation buffer, and continuously outputs an index suppression signal from when the erase instruction signal is received until the erase is completed. Address conversion buffer erasure control unit), and when the index suppression signal from the address conversion buffer erasure control unit is invalid, the translation information of the address translation buffer is indexed with the logical address output by the instruction analysis unit, and the corresponding real address is read. A plurality of index control means (hereinafter referred to as an address conversion buffer index control unit) for taking out an address, stopping the index of the conversion information in the address conversion buffer when the index suppression signal is valid, and waiting for the index suppression signal to become invalid. It is provided for each of the existing processors.

[0005]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention is:
The main memory 1 shared by a plurality of processors, a logical page address and a real page address are stored in pairs, and the logical page address given via the line 16 is indexed by a logical page address. To signal line 1
7, an address conversion buffer 1 for receiving information on a logical page to be erased, which is provided via a line 19, and erasing a pair of the logical page address and a corresponding real page address.
4 and 24, analyze a given instruction, and if the instruction is an instruction involving reading / writing to / from the main memory 1, signal lines 15 and 2;
5 receives a conversion information erasing instruction for erasing a page address pair, which is the conversion information, from all the address conversion buffers in the information processing apparatus, and outputs an instruction signal to the line 3 to analyze these instructions. Instruction analysis units 11 and 21 for starting the analysis of subsequent instructions upon completion, and information on logical pages to be erased on lines 19 and 29 in response to an instruction signal given from the instruction analysis units 11 and 21 via line 3 , And outputs an index inhibition signal indicating that the address translation buffer is being erased to lines 18 and 28 until the end of the erasing operation.
And when the index suppression signal provided via lines 18 and 28 is invalid, the logical address provided via lines 15 and 25 is separated into a logical page address and a logical page address and a relative address within a page. The logical page address is output to 26, and the corresponding real page address provided from the address translation buffers 14 and 24 via lines 17 and 27 is combined with the separated relative address to form a real address and the main memory 1 via line 2 And an address conversion buffer for stopping the index operation to the address conversion buffers 14 and 24 and waiting for the index operation until the index inhibition signal becomes invalid when the index suppression signal applied via the lines 18 and 28 is valid. Index control sections 12 and 22 are included.

Next, the operation of one embodiment of the present invention will be described in detail.

The address translation buffers 14 and 24 are
In order to convert a logical address to a real address at high speed, a logical page address and information of a real page address corresponding to the logical page address are held in a pair.

The instruction analyzed by the instruction analyzer 11 is the main memory 1
When reading and writing are performed, the logical address is output to the address conversion buffer index control unit 12 via the signal line 15. The address conversion buffer index control unit 12 separates the logical address into a logical page address and a relative address within a page, and sends the logical page address to the address conversion buffer 14 via a signal line 16. If there is indexed matching information, the corresponding real page address is assigned to signal line 1
Return by 7. Address translation buffer index control unit 1
2 outputs the real page address to the main memory 1 via the signal line 2 by combining the real page address and the intra-page relative address.

Similarly, when the instruction analyzed by the instruction analyzer 21 involves reading and writing of the main memory 1, a logical address is output to the address conversion buffer index controller 22 via a signal line 25. Address translation buffer index control unit 2
2 separates the logical address into a logical page address and a relative address within a page, and sends the logical page address to the address translation buffer 24 via a signal line 26. Exists, the corresponding real page address is returned via the signal line 27. The address conversion buffer index control unit 22 combines the real page address and the relative address in the page and outputs the result to the main memory 1 via the signal line 2 as a real address.

The instruction analysis unit 11 or 2 accompanying the change of the table for managing the conversion from the logical address to the real address
When a translation information erasure instruction of the address translation buffer appears in step 1, the instruction analysis unit removes the information of the page specified by the instruction from all the address translation buffers in the information processing apparatus. 13 and 2
An instruction is issued to signal 3 via signal line 3 and the instruction is terminated to start processing of the subsequent instruction. The address conversion buffer erasure control units 13 and 23 send information on the logical page to be erased to the address conversion buffers 14 and 24 via the signal lines 19 and 29 independently of each other, based on the instruction from the signal line 3. At the same time, the fact that the address translation buffer is being erased is transmitted to the address translation buffer index control units 12 and 22 via signal lines 18 and 28, respectively. Address translation buffer 14
And 24 erase the information corresponding to the real page address of the logical page specified by the signal lines 19 and 29, respectively.
When the translation information erasure instruction of one address translation buffer is executed, the address translation buffer erasure control unit may instruct the address translation buffer to erase a plurality of logical pages.

[0012] During the erase address translation buffer erase control unit 13 or 23 is the address translation buffer, each address translation buffer index controller 12 and 2 2 stops instruction of the index to the address translation buffer. This allows
When the address translation buffer is indexed by an instruction subsequent to the translation information erase instruction of the address translation buffer, the information of the logical page to be erased is erased at the time of indexing, and the information is deleted from the logical address performed in the information processing device. The identity of the translation to the address is also guaranteed.

[0013]

As described above, according to the present invention, the execution time of the erase instruction in the processor in which the translation information erase instruction of the address translation buffer appears, and the execution stop of the instruction accompanying the erase of the address translation buffer in the other processors. By shortening the time or the instruction re-execution time, there is an effect of improving the instruction processing capability of an information processing device having a plurality of processors.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main memory 11 Instruction analysis unit 12 Address conversion buffer index control unit 13 Address conversion buffer erasure control unit 14 Address conversion buffer 21 Instruction analysis unit 22 Address conversion buffer index control unit 23 Address conversion buffer erasure control unit 24 Address conversion buffer

Claims (1)

(57) [Claims] 1. An information processing apparatus comprising a plurality of processors of a virtual storage system having an address translation buffer for holding translation information from a logical address to a real address, wherein each of the plurality of processors analyzes instructions. Instruction analysis means for outputting an erasure instruction signal when the instruction is a translation information erasure instruction of the address translation buffer, and outputting a logical address of the main memory when the instruction involves reading and writing of the main memory; Erasing means for erasing information relating to the logical address designated by the erasing signal from the address translation buffer, and continuously outputting an index suppression signal from when the erasing instruction signal is received until erasure is completed; If the inhibit signal is invalid, the address translation buffer is translated with the logical address output by the instruction analysis means. Index control means for indexing information and extracting a corresponding real address, stopping the index of the translation information in the address translation buffer when the index inhibition signal is valid, and waiting for the index inhibition signal to become invalid. An information processing apparatus, characterized in that: