JPS6269339A - Address converting buffer system - Google Patents

Abstract

PURPOSE:To shorten an address converting time by improving the using efficiency of the information on an address converting buffer. CONSTITUTION:A TLB control part 32 does not invalidate a TLB 30 when the control is shifted to a virtual computer from a VM monitor. When the TLB 30 performs the address conversion, the logic page address of a register 12 and the VMID of a control register 10 are supplied to the part 32 together with the LPA of a control register 11. Then the part 32 retrieves a VMID part 17 coincident with the VMID, LPA and the logic page address, an LPA part 33 and a valid item 31 having a logic address part 18 through the TLB 30. When the corresponding item 31 is detected, the absolute address part 19 is defined as an absolute page address to set a conversion address to a register 20 as conventional. Thus the address converting time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] This is an address translation buffer (TLB) method in the execution of a multiprocessor virtual machine. When a virtual machine is a multiprocessor, it is necessary to control the address translation contents generated during execution by different logical processors so as not to use them. To this end, each item in the TLB holds the identification information of the virtual machine and logical processor that caused the conversion address pair, and when searching the TLB, this identification information is also referenced to perform the conversion operation. do.

With this configuration, unnecessary invalidation of TLBs can be reduced and execution efficiency can be improved.

[Industrial application field]

The present invention relates to an address translation buffer system in the execution of a multiprocessor virtual machine in a computer system.

In a computer system, a method of operating one or more other virtual computer systems, so-called virtual computers, is well known.

In that case, each virtual computer is under the control of the virtual computer control program (hereinafter referred to as VM monitor) of the real computer system, and the virtual computer to which control is transferred by the VM monitor is the central processing unit of the real computer. It is executed by a device (hereinafter referred to as "actual unit...").

The logical address generated by the execution of a virtual machine is
Access to the storage device is performed by converting the address into an absolute address. In order to speed up this address conversion process, each real processor is provided with a known address conversion buffer (hereinafter referred to as B). A method is adopted in which pairs of logical addresses and absolute addresses are stored.

In this case, since the logical address is a local address for each virtual machine, it is necessary to identify the virtual machine using the TLB.

Furthermore, as virtual machines have come to be executed in a multiprocessor configuration, it has become necessary for TLR control to identify the so-called logical processors that make up the multiprocessor.

(Prior Art) FIG. 2 is a block diagram showing an example of the configuration of a computer system.

The plurality of real processors 1 are connected to the main storage device 3 via the storage control device 2, and are connected to the main storage device 3 through the storage control device 2. Execute the program loaded into the α device 3.

As is well known, each of one or more virtual machines is under the control of a VM monitor, which is a management program for a real computer system, and the VM monitor selects one real processor 1 and transfers control to start execution. do.

FIG. 3 is a block diagram showing the configuration of the address translation mechanism of each real processor 1. As shown in FIG.

When passing control to a virtual machine, the VM monitor sets a virtual machine identification name (hereinafter referred to as VMID) in the control register 10 of the real processor.

Further, the control register 11 is set with the logical processor identification address (hereinafter referred to as LPA) of the logical processor that constitutes the virtual machine.

When a logical address generated for main memory access of a virtual machine is set in the register 12, the upper part of the logical address (logical page address) and the control register 10, excluding the intra-page displacement of the lower part, for example. V? I
ID is input to the TLB control unit 13, and address translation by the TLB 14 is attempted.

As is well known, each term 15 of the TLB 14 has a valid bit 16 that indicates the validity of the content of the term, and a VMI that holds the VMID.
The TLB control unit 13 has a logical address unit 18 that holds a logical page address, and an absolute address unit 19 that holds a page address of a page area on the main storage device 3. V old 1] and a valid term 15 having a V old part 17 and a logical address part 1 day, which have one loss in the logical page address, are searched.

If there is a corresponding term 15, the absolute address part 19 is set in the upper part of the register 20 to make it an absolute page address, and the intra-page displacement of the register 12 is connected to the lower part, thereby completing the address conversion.

As a result of the search by the TLB control unit 13, if there is no corresponding term in the above sense, the address conversion control unit 21 is started and the address conversion table held in the main storage device 3 is used. Address translation is performed by

In this address conversion, for example, a virtual real page address for the main memory on the virtual machine is first obtained, and the prefix processing unit 22 converts this virtual real page address into
When prefix processing is performed, the main memory of the real computer 3
The result is set in the register 20 to obtain the same converted address as above.

Also, under the control of the TLB control unit 13, 1 of the TLB 14
In the section, the absolute page address obtained by the current address conversion, the logical page address in the register 12 that should correspond to this, and the V old value in the control register 10,
Each is written in a predetermined part within one term.

As is well known, prefix processing is a system control information area unique to each processor that is individually provided on the main memory 3 in a multiprocessor configuration, and each processor accesses its own area using the same system control information area. This function allows access using real addresses.

As a result, the absolute page address held in the absolute address section 19 of the TLB 14 generally has validity only after not only the virtual machine but also the logical processor has been identified.

[Problem that the invention seeks to solve]

For this purpose, conventionally, when control is passed from the VM monitor to a certain virtual machine as described above, before starting execution of the virtual machine, the control register 10 is set for the TLB 14.
It is activated after resetting the valid bits of the terms whose content matches the old value shown by ν and invalidating them all. Therefore, at least at the beginning of execution, the TLB 14 naturally has no valid term that can be used for address translation, and the address translation processing time is a factor in reducing the execution efficiency of the virtual machine.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the address translation mechanism of a real processor, and TLB
30, each item 31 contains the logical process identification address L.
An LPA section 33 that holds PA is added.

In searching for the TLB 30, the TLB control unit 32
The ID section 17, LPA section 33, and logical address section 18 are referred to.

[For production]

Control the virtual machine from the VM monitor as before.
TLB controller 32 does not invalidate TLB 30 when TLB 30 passes.

In the address conversion by the TLB 30, the logical page address of the register 12 and the VMID of the control register 10 are input to the B control unit 32 as in the conventional case.
LPA of control register 11 is input.

The TLB control unit 32 receives νMIO,LP from the TLB 30.
A and the VID section 17, L that matches the logical page address
Valid term 31 having a PA section 33 and a logical address section 18
Search for.

If there is a corresponding term 31, the absolute address field 19 is set as an absolute page address, and a converted address is set in the register 20 as in the conventional manner.

As described above, the efficiency of using the information held in the TLB is improved and the address translation processing time is shortened, so that the performance of the virtual machine can be improved.

〔Example〕

In FIG. 1, the TLB control unit 32 executes the same control as the conventional TLB control unit 13 except as described below.

Each term 31 of the TLB 30 has an LPA section 33 in addition to a valid bit 16, a VMID section 17, a logical address section 18, and an absolute address section 19, similar to the conventional TLB 14.

In the address conversion by the TLB 30, the TLB control unit 32 receives not only the logical page address of the register 12 and the VMID of the control register 10 as in the past, but also the LPA of the control register 11.

The TLB control unit 32 receives the VMID, L from the TLB 30.
V obsolete portion 17 that matches the PA and logical page address;
Effective term 3 having LPA section 33 and logical address section 18
1, and if there is a corresponding term 31, the absolute address field 19 is set as the absolute page address, and the converted address is set in the register 20 as in the conventional method.

TLB 30; t- If there is no term with the corresponding content after searching, address translation is executed by the address translation control unit 21, and if an absolute address is obtained as the output of the prefix processing unit 22, , TLB control unit 32
writes a translated address pair to one term of TLB 30.

In that case, the TLB control unit 32 writes the absolute page address actually obtained by address conversion, the logical page address in the register 12 that should correspond to this, and the V old 0 in the control register IO, as in the past. , simultaneously writes the LPA of the control register 11 into the LPA section 33.

As described above, different logical processors are identified during the search, so conventionally, for the purpose of erasing address translation pairs generated when different logical processors of the same virtual machine are executed,
The TLB 0) invalidation process that was performed when control was passed from the VM monitor to the virtual machine is no longer necessary.

As a result, TLB 30 invalidations are reduced and TLB
Since there is an increased chance that the usable translation information held in 30 can be used immediately, the address translation processing time can be shortened by improving the efficiency of using TLB information.

(Effects of the Invention) As is clear from the above description, according to the present invention, in a computer system running a virtual A1 computer with a multiprocessor configuration, the efficiency of using information in address translation buffers (TI, B) is improved. Therefore, there is a significant industrial effect of shortening the address translation time and improving the performance of the virtual machine.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a computer system, and FIG. 3 is a block diagram of a conventional configuration. In port 1, l is a real processor, 2 is a control device, 3 is a main memory, 10.11 is a control register, 12.2
0 is a register, 13.32 is a TLB control unit, 14.
30 is the address translation buffer (T1.B) 15. 31 is the Tl2O term, 16 is the effective pinpoint, 17 is the VMID section, 18 is the logical address section, 19 is the absolute address section, 21 is the address translation control section, 22 is the prefix Processing section, 33ba1, PA section Fig. 1 Block diagram of an example of a computer system Fig. 2 Block diagram of an example of a conventional configuration Fig. 3

Claims (1)

[Scope of Claims] In a computer system in which a virtual machine having a multiprocessor configuration consisting of a plurality of logical processors is operated by a real processor having an address translation buffer, each logical address (18) held in the address translation buffer (30) is provided. and an absolute address (19), and is configured to hold information (17, 33) identifying the virtual machine and the logical processor that have issued an access request to the logical address. An address translation buffer method characterized by: