JPS6269338A - Control system for address converting buffer - Google Patents

Abstract

PURPOSE:To improve the performance of a virtual computer by decreasing the number of times invalidation of an address converting buffer. CONSTITUTION:A logic processor display register 30 has such constitution where a single display bit is allocated to each logic processor and it is displayed by the display bit value '1', for example, that the corresponding logic processor is used. A logic processor detecting part 31 checks the display bits of all logic processors forming a virtual computer designated by the VMID of a control register 10 and resets the display bit value '1', if detected among the display bits excepting those decided by the LPA, to '0'. As a result, an invalidating process request is given to a TLB control part 32 as long as just a single display bit having value '1' is detected. In such a case, the part 32 invalidates each item of a TLB 14 having the same contents as the VMID of the register 10. Otherwise the part 31 informs no need for invalidation to the part 32 and no invalidation is carried out.

Description

[Detailed Description of the Invention] [Summary] This is a control method for an address translation buffer in the execution of a multiprocessor virtual machine. If the virtual machine is a multiprocessor, it is necessary to invalidate the address translation contents generated during execution of different logical processors so that they are not used. For this purpose, means for displaying the executed logical processor is provided corresponding to each real processor.

When a virtual machine starts running, it checks whether a different logical processor has been executed, and if so, invalidates all entries for that virtual machine in the address translation buffer and clears the display. With this configuration, unnecessary invalidations can be reduced and execution efficiency can be improved.

[Industrial application field]

The present invention relates to a control method for an address translation buffer in the execution of a multiprocessor virtual machine in a computer system.

In a computer system, a method of operating one or more other virtual computer systems, so-called virtual computers, is well known.

In that case, each virtual machine is a virtual machine control program (hereinafter referred to as VM monitor) of the real computer system.
The virtual machine that is under the control of the VM monitor and to which control has been passed is executed by the central processing unit (hereinafter referred to as a real processor) of the real machine.

The logical address generated by the execution of a virtual machine is
The main memory is accessed by converting the address into an absolute address. In order to speed up this address conversion process, each real processor is equipped with a well-known address translation buffer (hereinafter referred to as TLB). A method is adopted in which pairs of logical addresses and absolute addresses are stored.

In this case, since the logical address is a local address for each virtual machine, it is necessary for the method B to identify the virtual machine.

Furthermore, as virtual machines have come to be executed in a multiprocessor configuration, it has become necessary for B control to identify the so-called logical processors that make up the multiprocessor.

[Conventional technology]

FIG. 2 is a block diagram showing an example of the configuration of a computer system.

The plurality of real processors 1 are connected to the main storage device 3 via the storage control device 2, and execute programs loaded in the main storage device 3.

As is well known, each of one or more virtual machines is under the control of a VM monitor, which is a management program for a real computer system, and the VM monitor selects one real processor 1 and transfers control to start execution. do.

FIG. 3 is a block diagram showing the configuration of the address translation mechanism of each real processor 1. As shown in FIG.

When passing control to a virtual machine, the VM monitor sets a virtual machine identification name (hereinafter referred to as VMID) in the control register 10 of the real processor.

Further, the control register 11 is set with the logical processor identification address (hereinafter referred to as LPA) of the logical processor that constitutes the virtual machine.

When a logical address generated for main memory access of a virtual machine is set in the register 12, the upper part of the logical address (logical page address) and the control register 10, excluding the intra-page displacement of the lower part, for example. VMI of
T L B with D! ji to the control unit 13, and the TL
Attempt address translation using B14.

As is well known, each term 15 of the TLB 14 includes a valid bit 16 that indicates the validity of the content of the term, a V obsolete part 17 that holds a VMID, a logical address part 18 that holds a logical page address, and a corresponding main bit. The TLB control unit 13 has an absolute address section 19 that holds the page address of the page area on the storage device 3, and the TLB control section 13 has a valid address section 17 and a logical address section 18 that store the VMID and logical page address from the TLB 14. Search for item 15.

If there is a corresponding term 15, the absolute address part 19 is placed in the upper part of the register 20 to make it an absolute page address, and the intra-page displacement of the register 12 is connected to the lower part, thereby completing the address conversion.

As a result of the search by the TLB control unit 13, if there is no corresponding term in the above sense, the address conversion control unit 21 is started and the address conversion table held in the main storage device 3 is used. Address translation is performed by

In this address conversion, for example, a virtual real page address for the main memory on the virtual machine is first obtained, and the prefix processing unit 22 converts this virtual real page address into
The prefix is processed and converted to an absolute address in the main memory 3 of the actual computer, and the result is set in the register 20, Ai? Get the same translated address as above.

Also, under the control of the TLB control unit 13, 1 of the TLB 14
The absolute page address obtained by the current address translation and the corresponding logical page address and VMID are written in the column.

As is well known, prefix processing is a process in which an area for system control information unique to each processor is provided on the main memory 3 in a multiprocessor configuration, and each processor uses the same real address to access its own area. This is a function that allows access by.

As a result, the absolute page address held in the absolute address section 19 of the TLB 14 generally becomes valid only after not only the virtual machine but also the logical processor is identified.

[Problem that the invention seeks to solve]

For this purpose, conventionally, when control is passed from the VM monitor to a certain virtual machine as described above, before starting execution of the virtual machine, the control register 10 is set for the TLB 14.
It is configured to start after invalidating all items whose contents match the VMID indicated by . Therefore, at least at the beginning of execution, the TLB 14 naturally has no valid term that can be used for address translation, which lengthens the address translation processing time and becomes a factor in reducing the execution efficiency of the virtual machine.

[Means for solving problems]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the address translation mechanism of the real processor, where 30 is a logical processor display register that holds an indication of the executed logical processor, and 31 is the VMI of control register 10.11.
The logical processor display register 30 is controlled by using D and LPA as inputs, and the TLB control unit 32 is given TLB control based on the result.
This is a logical processor detection unit for instructing the invalidation of a required term of the LB 14 or the necessity of invalidation processing.

[For production]

When control is passed from the VM monitor to the virtual machine as in the past, the TLB control unit 32 performs T1. Activate the logical processor detection unit 31 without invalidating B14.

The logical processor detection unit 31 detects the VM of the control register 10.
The ID and LPA of the control register 11 set the corresponding bit of the logical processor display register 30.

The logical processor display register 30 is configured to allocate one display bit to each logical processor, and for example, a display bit value of "1" indicates that the corresponding logical processor is used.

The logical processor detection unit 31 detects the VM of the control register 10.
The display bits of all the logical processors constituting the virtual machine specified by the ID are checked, and if there is a display bit value "lo" other than the display bit determined by the LPA, it is reset to 0.

As a result of the above processing, at least 1 display focus is 1°
If there is a bit, the TLB control unit 32 is requested to perform invalidation processing. In this case, the TLB control unit 32 creates a TLB 14 with the same contents as the VMID of the control register 10.
Disable each section.

In other cases, the logical processor detection unit 31 detects the TL
The B control unit 32 is notified that invalidation is not necessary, and invalidation is not executed.

As described above, the chances of invalidating the TLB are reduced, and the performance of the virtual machine can be improved.

〔Example〕

In FIG. 1, the TLB control unit 32 executes the same control as the conventional TLB control unit 13 except as described below.

The logical processor display register 30 allocates one display bit for each virtual machine indicated by V old and for each logical processor indicated by LPA, and for example, the display bit value ``1'' indicates that the corresponding logical processor is used. This is a register configured to display .

When control is passed from the VM monitor to the virtual machine as in the past, the TLB1trllm unit 32 activates the logical processor detection unit 31 without invalidating the B14.

The logical processor detection unit 31 detects the VM of the control register 10.
The corresponding 1 display focus of the logical processor display register 30 is set by rD and LPA of the control register 11.

Next, the logical processor detection unit 31 detects the control register 10
In step 10, all display bits of the logical processor/fusers constituting the virtual machine specified in step 10 are checked.

Check the indication bits of the corresponding logical processor group, and
If there is a display bit value of 1° in addition to the set display bit determined by , it is reset to 0, and it is stored that there is a display bit with a display pitch of 1°.

The above process is performed for all display bits of the corresponding logical processor group, and as a result, at least one display bit is 1°.
If so, the TLB control unit 32 is requested to perform invalidation processing only in that case, and the TLB control unit 32 stores each item of the TLB 14 having the same content as the VMID of the control register 10 in the same manner as before. Disable.

In other cases, the logical processor detection unit 31 detects the TL
The B control unit 32 is notified that invalidation is not necessary, and invalidation is not executed.

As described above, invalidation of the TLB 14 is limited to cases where there is a possibility that absolute addresses related to different logical processors of the virtual machine to be started remain in the TLB 14, so the chances of invalidation are reduced. Virtual machine performance can be improved by reducing address translation efficiency degradation.

In the above explanation, the logical processor display register 30 is provided in the real processor for the display bit corresponding to the logical processor, but this may also be set as a table provided in an appropriate area of the main t9 device 3, for example. Alternatively, the table may be configured as a collection of tables for all real processors, variations of which can be easily implemented from the above description.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a computer system running a virtual machine with a multiprocessor configuration, the number of invalidations of the address translation buffer (TLB) is reduced, so that the efficiency of address translation is improved. This has a significant industrial effect of improving the performance of virtual machines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a computer system, and FIG. 3 is a block diagram of a conventional configuration. In the figure, 1 is a real processor, 2 is a storage control device, 3 is a main memory, 1o and 11 are control registers, 12.20 are registers, 13.32 are TLB control units, 14 is an address conversion buffer 21 is an address conversion 22 is a prefix processing unit; 30 is a logical processor display register; and 31 is a logical processor detection unit.

Claims (1)

[Scope of Claims] In a computer system in which a virtual machine having a logical multiprocessor configuration is operated by a real processor having an address translation buffer (14), each of the virtual machines executed by the real processor corresponds to each real processor. Means for displaying logical processors (30)
and when the real processor starts execution of the virtual machine,
Referring to the display means (30), if there is a display of a logical processor that is different from the logical processor that starts the execution of the virtual machine, the section that holds the address corresponding to the virtual machine in the address translation buffer is An address translation buffer control method, characterized in that the address translation buffer control method is configured to invalidate and erase the display.