JPH071489B2 - Computer device and method for detecting and correcting data inconsistency in a cache data array in a computer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of the Invention The present invention includes an operating system that allows each user to have multiple operating processes.
It relates to certain improvements in hardware and software in workstations using virtual addressing in a multi-user operating system with write-back cache. In this regard, for convenience of explanation, a specific multi-user, multi-operating process operating system, namely Unix (TM)
The invention will be described in the context of a (units) operating system. However, it is not limited to use in connection with the present invention operating system, and the claims are not to be construed as covering the present invention, which may be used only in a unit operating system. .

[Conventional technology]

On Unix-based workstations, one of the building blocks is virtual address writeback.
back) By including a cache, system performance can be greatly improved. However, in such systems, support for alias addresses (ie, two or more virtual addresses that map to the same physical address in real memory) becomes a problem.

Any data update to the write-back cache through one of two virtual addresses (two alias addresses) that are aliases of each other will result in the other alias address (the two alias addresses themselves I can't see it.

More specifically, the use of virtual addresses allows aliasing, that is, mapping of multiple virtual addresses to the same physical address. If a virtual address writeback cache is used that is directly mapped without page mapping limitation, any two virtual addresses can occupy any two cache locations and are mapped to the same physical address. . Even if the cache block is modified, it is usually not possible to check between any of the cache locations to keep the data consistent. When changes at one cache location are not visible at the other cache location, the result is inconsistent data. Eventually, the data at the physical address of the main memory only contains a part of the modifications made to the cache memory by the CPU or I / O device, which is a disadvantage.

[Outline of Invention]

In the present invention, the above problem is solved by combining two strategies for dealing with aliases.

The first strategy is that the lower address bits of the alias address are the same and the size of the cache is (minimum).
It is to create an alias address so that it can be changed. This strategy can be applied to all user programs that use alias addresses generated by the kernel or entirely in the kernel. Those alias addresses for this strategy are generated by modifications to the kernel and are not visible to user programs. The alias address so generated maps directly to the same cache within the mapped cache (one-way set association) or within the same set of multidirectional set association caches. .
The alias hardware detection logic is then used to ensure data consistency within this cache (or cache set).

The second strategy covers those alias addresses in the operating system that are not user programs that cannot be matched in the lower address bits. They are handled by assigning their pages as "non-cacheable" pages in the memory management unit (MMU) employed by workstations using virtual addressing.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram of a typical workstation using virtual addresses in which the present invention is implemented.

In particular, the workstation is a microprocessor or central processing unit (CPU) 11, a cache data array 19, a cache tag array 23, a cache comparator 25, a memory management unit (MMU) 27, and a main memory. 31 includes a write back buffer 39 and a work station control logic 40. The workstation, if desired, has a context ID register 32,
A cache flash logic 33, a direct virtual memory access (DVMA) logic 35, and a multiplexer 37 may also be included.

In addition to the above elements, a multiplexer 45, an alias detection logic 47, an alias detection control logic 49, and a real address register 51 are further required to implement the present invention. The device supports alias addresses without the problems inherent in the prior art that utilizes virtual address writeback caches.

Each of these elements will be described, including the changes that must be made to the core of the operating system, and with particular emphasis on the parts unique to the present invention.

DESCRIPTION OF REQUIRED DEVICES FOR WORKSTATION The CPU 11 causes bus cycles to address instructions and data (following address translation) in memory and possibly other devices. The CPU address itself is a virtual address of size (A) bits that uniquely identifies a byte of instruction or data within the virtual context. A bus cycle can be characterized by one or more control fields that uniquely identify the bus cycle.
In particular, read / write indicators are required, as well as "type" fields. The field identifies the instruction and data address space of the memory as well as the access priority for the bus cycle (ie, "supervisor" or "user" access priority).
MC 68020 is a CPU that can be used in a workstation that has virtual addressing and can support a multi-user operating system.

Another necessary element in the virtual address workstation shown in FIG. 1 having a write-back cache is the virtual address cache data array 19. It is organized as an array of ^2N data blocks. Each data block contains 2 ^M bytes. 2 ^M bytes in each block is uniquely identified by a lower M address bits. Each of the 2 ^N blocks is uniquely addressed as an array element by the next N lower address bits. As the virtual address cache, the addressing byte of the (N + M) bit in the cache is (A + C).
It is from the bit's virtual address space. (As described below, the (C) bit is the context bit from the context ID register 32 used by the selection.)
The (N + M) bit is an added virtual bit from the (A + CP) bit that defines the virtual page address to the (P) untranslated page bits.

Virtual address cache data array 19 described here
Is a "mapped directly" cache or a "one way set association" cache. This cache configuration is used for the purposes of explaining the present invention, but it is not meant to limit the scope of the invention and may be used in connection with a multi-directional set associative cache.

Another required element shown in FIG. 1 is a virtual address cache tag array 23 with one tag array element for each data block in the cache data array 19. Therefore, the tag array includes 2 ^N elements. As shown in FIG. 3, each element has an effective bit (V).
, Modified bit (M), two protection bits (P), virtual address field (VA, C if desired)
X) and. The protection bit (P) is composed of a supervisor protection bit (Supvsr Prot) and a write permission bit. The contents of the virtual address field uniquely identify the entire virtual address space of the (A + C) bit, as well as the cache tag and the lower address bits used to address the data array. That is, the tag virtual address field must include (A + C)-(M + N) virtual address bits.

The cache "hit" logic 25 compares the virtual access address with the contents of the virtual address cache tag address field. Within the access address, the lower M
The bit addresses the byte in the block, the next lower N bits address the block in the cache, and the remaining ((A + C)-(M + N)) bits are tagged as part of the cache "hit" cycle. Compare with virtual address field.

The cache "hit" logic must identify access to user instructions and data and supervisor instructions and data to systems that share an operating system. The definition of a "hit" that meets those requirements is shown in Figure 2a. The figure shows a comparator
20, Angate 22, Orgate 24, Andgate
26 is shown.

MMU27 that translates addresses in virtual space to physical addresses
Is another required element. The size of MMU27 is (2 ^P )
It is constructed based on pages of bytes. The pages are organized into segments of size (2 ^S ) bytes. In-page addressing requires a (P) bit. Those (P) bits are physical address bits that do not require translation. The role of MMU27 is to set the virtual page address bit ((A + C-P) or (A-P)) to (M
M) Translate to the physical page address of the bit. Then, the composite physical address is the (MM) page address bit. In this case, the number of bits per page is (P) bits.

The MMU 27 is a place for protection checking, ie, comparing access bus cycle priorities with the protection assigned to a page. To illustrate this, there are two types of protection that can be assigned to a page: a supervisor / user access identifier and a write protect / write permission identifier. Although the invention is not limited to such kind of protection, given this page protection, a "user" priority bus cycle accesses a page with "supervisor" protection or "write".
If a bus cycle accesses a page that has a "write protect" indication, a "breach of protection" may result.

The application of the MMU protection check via the MMU is shown in Figure 2c. In this figure, an inverter 28 and AND gates 30a, 30
b, OR gate 34 and AND gate 36 are shown. Also, the concept of protection check with virtual address write-back cache can be extended to CPU cycles only for cache that does not access MMU. Such a cache-only protection logic is shown in Figure 2b. This figure shows an inverter 42, AND gates 44a and 44b, and an OR gate 46.
And AND gate 48 are shown.

Also shown in FIG. 1 is a main memory 31 which can be addressed in the physical address space. Control of main memory access is performed via the workstation control logic 40.

The write-back buffer 39 is a register containing one block of cache data loaded from the cache data array 19. When moving an existing cache block it is always loaded into the write buffer 39. This can be done because the cache block needs to be updated with new content, or because the block has to be flushed. In either case, in the revert cache, the state of the cache tag for an existing cache block determines whether this block should be written back to memory. If the tag indicates that the block is valid and has been modified, as described below, the block contents must be written back to memory 31 when the cache block is moved. A write-back buffer 39 temporarily holds the data before it is written to memory.

A work station control logic 40 controls the overall operation of the work station element shown in FIG. In the preferred embodiment, the control logic 40 is configured as several state machines. Those state machines are shown in FIGS. 4 and 6-8. These state machines will be described in detail below along with a description of the alias detection control logic 49. The alias detection control logic 49 can also be integrated into the workstation control logic in the preferred embodiment.

Description of Selective Elements of the Workstation The context ID register 32 is an optional external address register that contains another virtual address bit that identifies a virtual context or process. The register, including the C bit, identifies in total (2 ** C) active user processes. The size of the entire virtual address space is 2 ** (A + C).

An important part of this virtual address space of 2 ** (A + C) is the virtual address space occupied by the operating system. Since the operating system is common to all user processes, it is assigned to a common address space across all active user processes. That is, the (C) context bit has no meaning in modifying the address of a page in the operating system. Rather, for each active context, the operating system is assumed to be in a common exclusive area in the top of the virtual address space (2 ** A) bytes. User pages may not be included in this area. Therefore, the operating system page addresses for the two types of user processes are the same, and the processes for the two processes are different. All pages in the operating system are marked as having "supervisor" protection.

A workstation of the type that can utilize the present invention can also include a cache flash logic 333 to remove selected blocks from the virtual cache when reassigning virtual addresses.

In this specification, the cache flash cache logic
33 will only explain that it shows the virtual address, its role as a part in the write-back cache system. Given that a range of addresses (eg, virtual page addresses) is to be reallocated, all instances of addresses from that range are removed from the cache before the new address allocation can be made, or ""Flushu". If you disable the valid bit in the tag of the cache block and the block is fixed,
By writing the block back to the memory, the cache block "flashes".

In addition to the CPU 11 as a source of bus cycles, the workstation can include one or more external input / output (I / O) devices, such as the DVMA logic 35. Those external I / O devices can produce bus cycles. These bus cycles are performed in parallel with the CPU to access one or more "types" of virtual address space. The virtual address from the CPU 11 or the DVMA logic 35, together with the address in the context ID register 32, is called an access address.

Another optional element is the data bus buffer 37. In the preferred embodiment, the data bus buffer is implemented as two buffers to control the flow of data between the 32-bit bus and the 64-bit bus. These buffers are needed when the CPU data bus is 32 bits and the cache data array data bus is 64 bits.

Description of Elements Unique to the Workstation of the Invention As noted above, in the present invention, two strategies are utilized to solve the data consistency problem that results from alias addresses. Both strategies require interacting with the operating system and specialized cache hardware to ensure data consistency.

The first strategy requires that the lower address bits of all alias addresses that map to the same data be matched so that the data is cached, so that those addresses must use the same cache location. The present invention detects real-time address comparators to detect alias addresses in memory accesses that "miss" the cache, and to control cache data updates so that all alias addresses point to consistent data within the same cache location. The alias detection logic 47 is used.

Since the nuclear address operation module that implements this first strategy matches the lower address bits of the alias address, the alias address is guaranteed to use the same cache location. If the cache size is 2 ^M data blocks (each data block is 2 ^N bytes), then at least the lower (N + M) bits of the alias address must match. This also applies to alias addresses within the same process and aliases between processes. As long as this requirement is satisfied, the alias address maps to the same cache block in the cache that is mapped directly, and the alias address maps to the same cache set in the multi-way set associative cache. The second strategy is
Prevents data from being cached by using the "not cached" bit defined for each page in the MMU27. In other words, each page descriptor in MMU 27 has a "not cached" bit.
The bit controls whether the instructions and data from that page can be written to the cache. If this control bit is set for a page, all data accesses to this page will be made directly to or from the memory, bypassing the cache. In bypassing the cache, the issue of virtual cache data consistency is avoided.

Alias dressing is possible, so one MMU
If a page in a page entry is marked as "not cached", then all alias page entries must be marked as "not cached". Otherwise, data consistency cannot be guaranteed.

Since alias address generation for user processes is controlled via the kernel, all user processes utilize the first strategy to ensure data consistency between alias addresses. However, some addresses for the operating system cannot be changed to meet the addressing requirements of the first strategy.
Instead, their system alias addresses are
It is handled by the second strategy, namely the assignment to the "no cache" page.

The following is a functional description of what is needed to produce data consistency in a directly mapped virtual address writeback cache using a combination of two strategies.

If the memory access cycle of CPU11 or DVMA35 "misses" the cache, the access virtual address is
Translated by MMU. The MMU's translation determines whether the page being accessed is a "non-cacheable" page and whether the access has a breach of protection. If the access is valid and it is for a page that can be cached, the cache is updated with the cache block corresponding to the access address.

Look up the current contents of the cache at the location corresponding to the access address to find possible alias addresses. If the current cache block is valid and has been modified, then the translated address of the cache block is compared to the translated access address to determine the source of valid data and update the cache.

The real address comparison performed by the alias detection logic 47 includes the translated bus cycle access from the real address register 51 and the translated cache address.
Taken as input from MMU27.

If the current cache block is valid and the translated addresses are the same, then the access address and the cache block address are aliases. If the cache block was modified, the current cache data is the most current data and the main memory data at this address is old.

The translated addresses are equal to each other, but if the cache block is not modified, the old cache data and the memory data are the same and both can be used as sources for cache updates.

Once the source of valid block data has been determined, the access cycle can be terminated. In the read cycle, following the cache update, the bus cycle returns data directly from the source or cache depending on the implementation. In the write cycle, access data can be written to the cache. Changing the cache size and aligning the cache data is implementation dependent.

To ensure data consistency, any write to a page, all relationships to that page (read or write) adhere to this constraint.

A preferred embodiment of the address path including the alias detection logic 47 is shown in FIG. As shown in FIG. 3, the address path includes the basic elements that support address control in the virtual address writeback cache. A virtual address register 52 (VAR) for virtual addresses (CX and VA) and a cache block valid bit (V) for alias address support, a multiplexer 45 for multiplexing the virtual address and the virtual address register, and Address register 51, alias detect logic 47, AND gate 53 (having valid bit from VAR and alias detect logic output as inputs), and address match flip-flop 55 that is set when a real address match is detected.
Is also needed.

The data path from the cache 19 to the main memory 31 is via two 64-bit buses 56,58. CPU data path 60 is 32 bits and is shown as D (31: 0). In the read bus cycle, which of the two 3-bit buffers 37 is a 32-bit CPU is a 64-bit cache and the data from the data bus 56 is a 32-bit CPU.
The cache address bit A (2) selects whether it can be placed on the data bus 60. The alias detection logic 49 controls the source of the data in the read cycle cache miss (cache or memory) and controls whether the cache is updated with the memory data in the write cycle cache miss (FIGS. 6 and 7). Data state machine).

Not all control lines are shown in FIGS. 3 and 5 to avoid unnecessary confusion in the figures. However, the control lines needed to operate the invention properly are:
This can be seen from the flow diagram of the state machine shown in FIGS. 4 and 6-8.

The following abbreviations are used in the flow charts.

MUX-Multiplexer 45 Sel-Selection VA-Virtual address RA-Real address OE-Output enable Ack-Acknowledgment Cache Hit? -Cash "Hit" Did 25 detect a cache (Fig. 2a) Cache Protect Violation?-Control Did the logic 40 detect the cache protection violation (Fig. 2b) Memory Busy?-Was memory busy asserted? MMU Protect Viol?-Whether the control logic 40 detects the MMU protection violation (Fig. 2c) RAR-Real address Register 51 CLK-Clock Adr-Address Mem Adr Strobe-Memory 31 Address Strobe VAR-Virtual Address Register Mem Adr Ack? -Memory Address Acknowledge was asserted by Memory 31 Mem Data Strobe 0? -Memory Data Strobe 0 asserted Mem Date Ack 0?-Was memory data acknowledge 0 asserted? Mem Date Strobe 1?-Memory data strobe 1 was asserted. Sart or not Mem Data Ack 1? -Memory data acknowledgment 1 was asserted Clk Write Back Buffer-Clock write-back buffer 39 Real Adr Match? -Are real address match detected (flip-flop 55) Don't Catch Page? − Whether the control logic 40 detects a page that is not cached from the MMU 27 CPU Read Cycle? − Whether the CPU 11 is in the read cycle Clk Date Reg − Clock data register 61 Valid and Modified Write Back Data? − Control logic 4
0 is valid bit (V) and modified bit (M) detected Write to Don't Cache Page-Control logic 40 detected CPU write to uncached page Start No Cache Write? -Control logic 40 asserted cache no write start? Start Write Back Cycle?-Whether control logic 40 asserted write back cycle start A similar omission is used in the timing diagrams shown in FIGS. 9-11.

The address state machine shown in Figures 4a and 4b defines some of the controls associated with the address handling portion of the cache. The present invention is integrated by the clocking of the real address matching flip-flop 55 (state (o)). State (w)
Following successful transfer of all block data from memory 31, cache tag 23 is written as valid during state (w).

The data state machine shown in Figures 6a and 6b and Figures 7a to 7d defines certain controls associated with the data transfer portion of the cache. As shown, after state (g), a test for writing to an uncached page is performed. The handling of this write to memory is shown in the next state (i, dw) path in the data state machine. Following state (o), a non-cacheable page access (for read data at this time) is tested. The read control without cache takes a non-real address coincidence path up to the states (q.nr) and (u.nr). Here, the test for non-cacheable pages prohibits cache updates in states (s.nr) and (w.nr).

The writeback state machine shown in FIG. 8 defines the control of the writeback cycle to memory. Since the write-back control and the data path are independent of the cache access control and the data path,
The cycle can be executed in parallel with the CPU cache access. The "Memory Busy" signal causes the address and data state machines to wait until the end of the previous writeback cycle, as described below.

The write cache miss timing diagram shown in Figure 9a defines the overall timing of a CPU write bus cycle to a cacheable page in memory that misses cache. A cache hit and a protection check occur in cycle (c) of this figure.

Part of the mishandling sequence involves the loading of the current cache block that will be replaced by the writeback buffer 39 in cycles (i) and (m). The translated address for the current cache is also loaded into real address register 51 in cycle (o). In cycle (o), the real address match latch (flip-flop 55) is also clocked. Assuming that the current cache block is valid and modified from the previous CPU (or DVMA) write cycle, that cache will be as shown in the memory data bus timing diagram of Figure 11b and the writeback state machine of Figure 8. The cache block is written to the memory 31 in the write-back bus cycle.

Active real address match latch (flip-flop 5
5) means alias address match. If there is no alias match, the CPU write data is merged with the block data returned from memory in the first data transfer of the block read memory bus cycle. During cycles (q) to (u), the CPU write output enable control buffer 37 is active only for bytes to be written by the CPU, and the data register output enable control data register 61 is for all other bytes. On the other hand, it is active. During the second data transfer, in cycle (w), the data register output enable for all bytes is active.

Assuming there is an alias match, the CPU data is written to the data cache in state (s) and the data from memory 31 is ignored.

The non-cache page write shown in Figure 9b defines the overall timing of a CPU write bus cycle to memory for an access to the non-cache page. The cache hit that occurs in cycle (c) always indicates a miss (no hit).

The case of writing to a non-cacheable page is different from the case of cache miss for a cacheable page in that the cache is not updated by the CPU or memory data. The implementation uses special memory bus cycles to update the memory directly. The memory bus cycle is called a non-cache page write cycle (Fig. 11c). Note that in this case the real address match latch has no meaning.

The read cache miss timing diagram shown in Figure 10a defines the overall timing of a CPU read bus cycle to a cacheable page in memory that misses cache. The cachet and protective checks occur in cycle (c) in this figure.

Part of the mishandling sequence involves the loading of the current cache block that is replaced in writeback buffer 39 in cycles (i) and (m). The translated address for the current cache block is also loaded into the real address register 51 (cycle (o)).
In cycle (o), the real address match latch (flip-flop 55) is also clocked. Assuming the current cache is valid and has been modified from the previous CPU (or DVMA) write cycle, then as shown in the memory data bus timing of FIG. 11b and the writeback state machine of FIG. The cache block is written back to the memory 31 in the write-back cycle.

Active real address match latch (flip-flop 5
5) means alias address match. If there is no alias address match, data is bypassed to the CPU via the buffer 37 enabled by the control signal "CPU read output enable" which is active in the states (q) to (u), and the state (e) Data is read into the CPU by updating the cache at the same time. The memory is configured to always return "missing data" on the first 64 bit transfer and the next 64 bit transfer of a block read memory bus cycle. After the CPU read bus cycle data is returned, the CPU can perform internal cycles while the cache is being updated on the second data transfer from memory.

Assuming there is an ellirias address match, the data is read directly from the cache 19 to the CPU 11 and the data from the memory 31 is ignored.

The read from non-cache page timing shown in Figure 10b defines the overall timing of the CPU read bus cycle to memory for access to non-cache pages. The cache hit that occurs in state (c) always indicates a miss (no hit).

The case of reading from a non-cacheable page differs from the case of cache miss to a read from a cacheable page in that the cache is not updated with memory data. The implementation uses the same block read memory bus cycle as the cache-miss case (see memory data bus timing below). The real address match latch (flip-flop 55) has no meaning for this case.

The memory data bus timings shown in FIGS. 11a to 11c show the timings of the block read cycle, the write back cycle, and the write bus cycle to the uncached page, respectively. Since the size of the cache block is 128 bits, each cache update requires two data transfers. As mentioned above, CPU1
The 64 bits containing the data addressed by 1 are always returned on the first transfer of a block read bus cycle.
The "Memory Busy" control signal is active while it is used to inhibit the start of the next cache miss cycle until the previous writeback cycle can be completed.

When writing to a page bus cycle that is not cached, the 8-bit byte mark field sent during the address transfer stage of the cycle indicates which of the 8 bytes of data is updated in the memory 31 during the data stage. Establish.

In addition to the hardware described above, in order to support aliased dressing, one must modify the core of the operating system in two basic ways:

1) The operating system utility that generates the user alias address must be modified to protect that the lower (N + M) address bits of the alias address meet a rule that, at a minimum, must match. I won't.

2) An example of an alias address in the operating system that cannot match the rule for matching lower (N + M) bits must be assigned to the "no cache" page.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main parts of a workstation using a virtual address with a write-back cache,
Fig. 2a is a schematic diagram of the cache "hit" logic, Fig. 2b is a schematic block diagram of the circuit for detecting the violation of the cache protection, Fig. 2c is a schematic block diagram of the circuit for detecting the violation of the MMU protection, and Fig. 3 is 4a, a detailed block diagram showing the address paths utilized by the alias detection logic of the present invention.
Figures 4a and 4b are a flow chart of the implementation of a state machine of some control related to the addressing of the virtual address writeback cache, and Figure 5 is a detailed block diagram showing the data paths utilized by the alias detection logic of the present invention. Figure and 6b
The figure is a flow chart (states (a) to (o)) of the state machine realization of some control related to the data transfer to and from the virtual address writeback cache, and Figure 7a shows the data path when a real address match exists. Flowchart of state machine for realization (states (q) to (u)), FIG. 7b shows flow chart of state machine for realization of data path when real address match does not exist during CPU write bus cycle (state (Q) (y)), the
Figure 7c is a flow chart of the state machine (states (q) to (y)) for implementing the data path when there is no real address match during the CPU read bus cycle, and Figure 7d is the MMU does not cache pages. Sometimes a state machine flow diagram for implementing a data path during a CPU write bus cycle, Figure 8 a state machine implementation flow diagram for controlling a write-back bus cycle to memory, and Figure 9a shows the pages that the MMU can cache. Sometimes a timing diagram for the best case for a CPU write bus cycle, Figure 9b shows a page where the MMU does not cache, and a timing diagram for the best case for a CPU write bus cycle, Figure 10a shows a page where the MMU can cache. Sometimes a timing diagram for the best case for a CPU write bus cycle, Figure 10b shows a CPU write when the MMU shows pages that are not cached Figure 11a shows the timing diagram of the memory bus cycle that realizes the block read cycle, Fig. 11b shows the timing diagram of the memory bus cycle that realizes the write-back cycle, and Fig. 11c does not cache. FIG. 9 is a timing diagram of a memory bus cycle for performing a page write. 11: Central processing unit, 19: Cash data array,
23 …… Cache tag array, 25 …… Cache hit comparator, 27 …… Memory management unit (MMU), 31 …… Main memory, 32 …… Context identification register, 33 …… Cache flash logic, 35… … Direct virtual memory access (DVMA) logic, 37,45 …… Multiplexer, 39
...... Write-back buffer, 40 …… Work station control logic, 47,49 …… Alias detection control logic, 51 ・ ・ ・
… Real address register, 52,54 …… Virtual address register, 60 …… Comparator, 61 …… Clock data register.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Gioseph Moran United States 95054 Santa Clara Wildwood Way 544 California (72) Inventor William Canon United States 94022 Los Altos Trianon Way 261 California (72) ) Inventor Ray Chien USA 95014 California State Cooperchino Summerset Court 10402 (56) Reference JP-A-63-53889 (JP, A) JP-A-54-148329 (JP, A)

Claims (4)

[Claims] 1. A central processing unit (CPU) executing an operating system, allocating resources and using alias addresses for at least one running process, and a central processing unit (CPU) for executing the process and the operating system. A virtual address cache tag array (CTA) coupled to a processing unit (CPU) for identifying cached virtual memory blocks, and coupled to the central processing unit (CPU) for identification A virtual address / writeback cache data array (CDA) that caches a virtual memory block, and a memory management unit (MM) that is coupled to the central processing unit (CPU) and translates a virtual address into a physical address.
U), a main memory (MM) that is coupled to the central processing unit (CPU), and stores a currently resident virtual memory page, and the central processing unit (CPU) and the cache tag array (CTA). A cache hit detector (CHD) that is coupled to detect a cache hit, the central processing unit (CPU), the cache tag array (CTA), the cache data array (CDA), the memory management unit (MMU). ), The main memory (MM), and the processor control logic coupled to the cache hit detector (CHD) to control their operations: a) a first virtual address and a second virtual address; Virtual address is
If they are aliases to each other, but do not belong to a given set of virtual addresses as described below, the operating system assigns the first virtual address and the second virtual address to their lower n + m bit parts. , So that one cache location is used for cache operations of the first virtual memory location and the second virtual memory location, and the first virtual address and the second virtual address are Identifying a second virtual memory page and a second virtual memory location within the memory page, respectively. The second virtual address comprises a second plurality of virtual address bits, and the first virtual address and the second virtual address are memory pages of the main memory (MM). And a predetermined virtual address set is translated into the same physical address composed of a plurality of physical address bits that identify the memory location within the memory page and the predetermined virtual address set. Of each virtual address in the given subset is an alias with any other virtual address in the given subset, and the cache tag array (CTA) is a cache The cache data array (CDA) has n cache blocks each having m cache positions, and the cache data array (CDA) has n cache blocks that specify n virtual memory blocks. B) virtual memory pages, wherein Virtual address
The memory management unit (MMU) marks the virtual memory page as a non-cacheable page if it includes at least one virtual address location specified by one virtual address of the set;
Therefore, the cache operation of the virtual memory block of the marked virtual memory page is prohibited, and all data accesses of the marked virtual memory page bypass the cache data array (CDA) and the main memory (MM). A computer device characterized in that it is performed directly between and. 2. The computer apparatus according to claim 1, wherein the memory management unit (MMU) is configured to identify at least one virtual address position specified by one virtual address of the predetermined virtual address set. The containing virtual memory page is marked by setting a bit in the page descriptor for the virtual memory page, and the virtual memory page descriptor describing the corresponding virtual memory page is the memory management unit (MMU). ) Is included in a plurality of computer devices. 3. A central processing unit (CPU) executing resources for an at least one process running and using an alias address, the central processing unit (CPU) executing the process and the operating system, A virtual address cache tag array (CTA) coupled to a processing unit (CPU) for identifying cached virtual memory blocks, and coupled to the central processing unit (CPU) for identification A virtual address / writeback cache data array (CDA) for caching virtual memory blocks, and a memory management unit (MM) that is coupled to the central processing unit (CPU) and translates virtual addresses into physical addresses.
U), a main memory (MM) that is coupled to the central processing unit (CPU), and stores a currently resident virtual memory page, and the central processing unit (CPU) and the cache tag array (CTA). A cache hit detector (CHD) that is coupled to detect a cache hit, the central processing unit (CPU), the cache tag array (CTA), the cache data array (CDA), the memory management unit (MMU). ), The main memory (MM), and a processor control logic coupled to the cache hit detector (CHD) to control their operation, and a data mismatch of the cache data array (CDA). A method of detecting and correcting the following: a) the first virtual address and the second virtual address are
If they are aliases to each other, but do not belong to the predetermined virtual address set described below, the first virtual address and the second virtual address are assigned to their lower n +
modifying the m-bit portions to be equal so that one cache location is used for cache operations of the first virtual memory location and the second virtual memory location, and the first virtual address and the second virtual memory location are used. The second virtual address is the identification of the first virtual memory page and the first virtual memory location within the memory page, and the second virtual memory page and the second virtual memory location within the memory page. Each of the first virtual address and the second virtual address, and the first virtual address and the second virtual address are the memory page of the main memory (MM) and the memory page in the memory page. Is translated into the same physical address composed of a plurality of physical address bits identifying a memory location, and the predetermined virtual address set is A predetermined subset of virtual addresses in the operating system's address space, each virtual address in the predetermined subset is an alias with any other virtual address in the predetermined subset; (CTA) has n cache tag entries that identify n cached virtual memory blocks, and the cache data array (CDA) has n cache blocks each having m cache positions. With n virtual memory blocks, and b) the virtual memory page has the predetermined virtual address
Comprising a make-up step of marking said virtual memory page as a non-cacheable page if it contains at least one virtual address location identified by one virtual address of the set, and
The cache operation of the virtual memory block of the marked virtual memory page is prohibited, and all data accesses of the marked virtual memory page bypass the cache data array (CDA) and the main memory (MM).
A method for detecting and correcting a data discrepancy in a cache data array in a computer device, which is characterized by being directly performed between the computer device and the computer. 4. The method according to claim 3, wherein the marking step comprises setting a bit in a page descriptor for the virtual memory page in the memory management unit (MMU). A plurality of virtual memory page descriptors describing corresponding virtual memory pages are included in the memory management unit (MMU), and a data mismatch in the cache data array in the computer device is detected. And how to fix.