JPH1124995A - Tlb access control system for address conversion - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TLB access control system for address conversion, which can simultaneously execute regular memory access and table access at the time of TLB(translation look aside buffer) mishit and which can realize a high speed processing. SOLUTION: A TLB table which is previously provided on a main memory 5 is provided in a private register 3. A TLB 30 is retrieved in response to a memory access from a DMA(direct memory access) controller 4. When TLB mishit occurs, the TLB table of the private register 3 is referred to instead of referring to the main memory 5. Thus, high speed processing is realized without waiting for TLB table reference even if contention with regular memory access by CPU 1 occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a TL for address conversion.
Regarding the B (Translation Look a side Buffer) access control method, in particular, a logical address from a DMA (Direct Memory Access) control unit is converted into a physical address by a TLB for address conversion, and a main memory is accessed by the physical address. The present invention relates to an address conversion TLB access control method in an information processing system.

[0002]

2. Description of the Related Art FIG. 3 shows a block diagram of a conventional TLB access control system for address conversion of this kind. As shown in FIG. 3, the system includes a CPU (central processing unit) 1
A main memory 5 accessed by the CPU 1 and the DMA controller 4; a DMA controller 4 controlling access to the main memory 5 from an I / O device (not shown); and a main memory 5 from the CPU 1 and the DMA controller 4. And a control unit 2 for controlling each access to.

The control unit 2 includes an IO buffer 21 for temporarily storing data and addresses between the CPU 1 and the control unit 2.
And an address buffer 23 for storing a memory address from the CPU 1, a main memory 5 and a base register 26.
A data buffer 22 for storing write data to the CPU and the like and response data to the CPU 1;
Controller 25 for controlling the TLB table and a TLB table (not shown) in the main memory 5 when a TLB mishit occurs
TLB that stores TLB data obtained by access
(I / O cache tag) 30 is compared with the logical address at the time of DMA access and the logical address in TLB 30.
A comparison and TLB address generation circuit 27 for generating a TLB address (physical address) for accessing the LM table, a TLB base register 26 used as a pointer when generating the TLB address, and an address buffer for storing a logical address 28.

Next, the operation of the conventional system will be described. First, the first address of the table area is set from the CPU 1 to the TLB base register 26 in the control unit 2.
Next, a table area is set on the memory 5, and TLB data is set as mapping information corresponding to a transfer area for DMA access.

When a logical address (32 bits) is issued to the address bus S10 in response to a DMA request from the DMA controller 4, the control unit 2 takes this logical address into an internal address buffer 28. TLB30
Has eight logical tags 301 and eight physical tags 302 therein.

The bit assignment of the logical tag 301 is 31
The logical address is defined at the -12th bit, the offset address (O) is defined at the 11th to 6th bits, and the valid bid (V) is defined at the 0th bit. The 5-1st bit is undefined (R).

The bit assignment of the physical tag 302 is 30
The physical address is defined at the -12th bit, the offset address (O) is defined at the 11-6th bit, and the valid bit (V) is defined at the 0th bit. The 5-1st bit is undefined (R).

[0008] The comparison circuit 27 compares the logical address stored in the address buffer 28 with the logical addresses of all the entries in the TLB 30 whose valid bid (V) is “1”.

[When the logical address of TLB is not hit (at the time of a mishit)] Even if the valid bit (V) in all the entries is "0" or the valid bit in the entries is "1", as a result of the comparison, If the logical addresses do not all match, the TLB address generation circuit 27
An address is generated, and TLB reading is performed on the TLB table area on the main memory 5.

[0010] As shown in FIG. 4A, the TLB address is generated by setting the TLB after setting by the CPU 1 in the 30th to 23rd bits.
The value of the 30th to 23rd bits of the B base register 26 is used as it is, and the DMA controller 4
Of the TLB base register 26 and the value of the 22nd to 3rd bits of the TLB base register 26 (the TLB base register 1).
The first to third bits and the 31st and 2nd bits of the TLB address are fixed to 0).

The 30th to 12th bits in the TLB data obtained by the TLB read are assigned to the physical tag 3 in the TLB 30.
02 is stored in the physical address 02, and its valid bit (V) is set to "1". At this time, the logical address from the DMA controller 4 is also stored in the logical address of the logical tag in the TLB 30 and its offset address (O), respectively, and its valid bit (V) is set to "1". The above is the TL when the TLB missed
B table access.

Next, a physical address is generated in the TLB 30, data for the TLB entry is loaded from the main memory 5 into an I / O cache (not shown), and in response to a request from the DMA controller 4, Responds by reading or writing the O-cache.

In the physical address generation, as shown in FIG. 5B, the physical address in the TLB 30 is used as it is in the 30th to 12th bits, and the logical address corresponding to the DMA request from the DMA controller 4 is directly used in the 11th to 6th bits. It is realized by using.

[When Matching to TLB Logical Address]
If the logical addresses match, then the comparison circuit 27
Logical address (11-6) from A controller 4 and T
The offset address of the logical tag in the LB 30 (11-
6).

As a result of the comparison, if the offset addresses match, an I / O cache (not shown) is directly read or written in response to a DMA request from the DMA controller 4.

If the offset addresses do not match,
A physical address is generated in the TLB 30, data for one entry of the I / O cache is loaded from the main memory 5 into an I / O cache (not shown), and a response is made to a DMA request from the DMA controller 4. At this time,
The logical address from the DMA controller 4 is stored in the TLB 30
Address (11-6) of logical tag 302 within
To store.

When a memory access request to the main memory 5 is issued from the CPU 1, when an address and write data for the main memory 5 are issued to the address / data bus S1, the control unit 2 controls the internal address / data buffer 23. / 22.

The address stored in the address buffer 23 is a RAS (row address strobe) generated by a controller 25 for controlling the main memory 5 and a CAS.
(Column address strobe) and WE (write enable) are output to the main memory 5 together with each signal, thereby performing memory access.

FIG. 5 is an example of a timing chart showing a memory & TLB access contention operation timing in the block diagram shown in FIG. The block names and signal names in FIG. 5 are equivalent to those in FIG.

At the same time (CLK1), a memory read request from the CPU 1 to the main memory 5 and a DMA request from the DMA controller 4 are transmitted at the same time (CLK1).
When the address is issued to 10, the address is stored in the IO buffer 21 and the address buffer 28 at the rising edge of CLK2.

The address stored in the IO buffer 21 is stored in the address buffer 23 at the rise of CLK3, and is simultaneously output to the controller 25 that controls the main memory 5.

On the other hand, at the same timing, the address buffer 2
8 is compared with the logical address in the TLB 30 and the result does not match.
The B address is generated (determined after CLK3). The generated TLB address is output to the controller 25 that controls the main memory 5 at the timing of CLK3.

Controller 2 for controlling main memory 5
5 receives the output address from the address buffer 23 and the TLB address at the timing of CLK3, giving priority to the output address from the address buffer 23,
The output of the row address to the main memory 5 is started from the rising edge of CLK4, and the main memory is accessed.

In the TLB table access at the time of a mishit in the TLB 30 for the DMA request from the DMA controller 4, the processing for the memory read request from the CPU 1 ends (response data from the main memory 5 is stored in the data buffer 22). Until the controller 25 that controls the main memory 5
The process is restarted from the timing of K12, and ends when the TLB data is stored in the TLB 30 at the rise of the CLK17.

An example of such a TLB access control method for address conversion is disclosed in Japanese Patent Application Laid-Open No. Hei 6-119247.

[0026]

As described above, TL
When a B-miss occurs, a TLB table or an address conversion table provided on the memory is referred to. Therefore, during a normal memory access (memory access from the CPU 1), if a table access request at the time of a TLB mishit occurs due to another process, the table access request will be kept waiting.

It is an object of the present invention to provide an address conversion TL capable of performing high-speed processing by simultaneously executing a normal memory access and a table access at the time of a TLB mishit.
B access control method.

[0028]

According to the present invention, a DMA is provided.
(Direct memory access) An address conversion T in an information processing system in which a logical address from a control unit is converted into a physical address by an address conversion TLB and a main memory is accessed by the physical address.
An LB access control system, wherein the storage means which is provided separately from the main memory and stores a physical address corresponding to the logical address in advance, and the address conversion TLB is searched by a logical address from the DMA control unit. An address conversion TL comprising: an index unit for generating the search result; and an access unit for accessing the storage unit when the index result indicates a mishit.
The B access control method is obtained.

When the index result indicates a mishit, the physical address obtained by accessing the storage means by the access means is converted to the address conversion T address.
An address translation TLB access control method is further characterized by further including control means for controlling writing to the LB.

The operation of the present invention will be described. A TLB table (correspondence table between a logical address and a physical address) conventionally provided in the main memory is provided in a dedicated storage device physically separate from the main memory, and the TLB table is referred to at the time of a TLB mishit. Can be performed independently of CPU access to enable parallel access.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and the same parts as those in FIG. 3 are denoted by the same reference numerals. FIG.
3 will be described. Only a portion different from the conventional example of FIG. 3 will be described. A dedicated register 3 is provided in addition to the main memory 5, and a dedicated register controller 29 is provided for controlling the dedicated register 3. It is assumed that the dedicated register 3 has an area capable of storing a TLB table whose storage area has been secured in the main memory 5.

An address decoder 24 for decoding the address from the CPU 1 and selecting the main memory 5 and the dedicated register 3 is also provided.

T is added to the newly provided dedicated register 3.
To set the LB table, first, the CPU
1 to the start address of the TLB table area in the TLB base register 26. The addresses for the dedicated register 3 are sequentially allocated based on the start address. However, an address assigned to the dedicated register 3 does not overlap the address space of the main memory 5.

Next, the TLB data, which is mapping information corresponding to the transfer area for the DMA access, is set by the CPU 1 by a write access to the dedicated register 3, and the setting to the dedicated register 3 is completed.

The operation of the system of this embodiment is equivalent to that of the prior art system except for operations other than the TLB table access at the time of TLB mishit at the time of DMA access and the access to the dedicated register 3.

When a TLB mishit occurs in response to a DMA request from the DMA controller 4, a TLB address generation circuit 27 generates a TLB address for a table area on the dedicated register 3 and sends the TLB address to a controller 29 which controls the dedicated register 3. Output. The generation of the TLB address is the same as that of the above-mentioned prior art system.

Controller 2 for controlling dedicated register 3
9 outputs the TLB address generated by the TLB address generation circuit 27 to the dedicated register 3 as it is.

When the dedicated register 3 receives a TLB address from the controller 29 that controls the dedicated register, the dedicated register 3 outputs TLB data corresponding to the TLB address.

The output TLB data is stored in the TLB 30 in the same manner as in the above-mentioned prior art system.
The handling of information (logical address, offset address, valid bit) stored in the TLB 30 other than the TLB data is the same as in the above-described prior art system.

FIG. 2 is an example of a timing chart showing a memory & TLB access contention operation timing of this embodiment.

The block names and signal names in FIG. 2 are equivalent to those in FIG.

At the same timing (CLK1), a memory read request from the CPU 1 to the main memory 5 and a DMA request from the DMA controller 4 are transmitted at the same time (CLK1).
When the address is issued to 0, the address is stored in the IO buffer 21 and the address buffer 28 at the rising edge of CLK2.

The address stored in the IO buffer 21 is stored in the address buffer 23 at the rise of CLK3, and is simultaneously output to the controller 25 that controls the main memory 5.

Controller 2 for controlling main memory 5
5 designates a row address for the main memory 5 as CLK4.
At the rise of CLK11 and ends by storing the response data from the main memory 5 in the data buffer 22 at the rise of CLK11.

On the other hand, at the same timing, the address buffer 2
8 is compared with the logical address in the TLB 30 and the result does not match.
The B address is generated (determined after CLK3). The generated TLB address is output to the controller 29 that controls the dedicated register 3 at the timing of CLK3.

Controller 2 for controlling dedicated register 3
9 receives the TLB address and outputs it to the dedicated register 3 at the same timing (CLK3). The dedicated register 3 outputs TLB data for the TLB address from the controller 29 that controls the dedicated register 3 at the timing of CLK3, and is stored in the TLB 30 at the rising edge of CLK4.

[0048]

As described above, according to the present invention, the TLB table (correspondence table between the logical address and the physical address) conventionally provided in the area on the main memory.
Is provided in a dedicated register, which is a dedicated storage means provided separately, so that normal main memory access from the CPU and access to the TLB table due to a TLB mishit can be processed in parallel. However, there is an effect that high-speed processing can be performed without waiting for access to the TLB table due to a TLB mishit.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the block in FIG.

FIG. 3 is a block diagram showing a conventional technique.

FIG. 4 is a diagram for explaining TLB address generation and physical address generation.

FIG. 5 is a timing chart showing the operation of the block shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Control part 3 Dedicated register 4 DMA controller 5 Main memory 21 IO buffer 22 Data buffer 23, 28 Address buffer 24 Address decoder 25 Memory controller 26 Base register 27 Comparison circuit & TLB address generation circuit 29 Dedicated register controller 30 TLB (IO Cache tag) 301 logical tag 302 physical tag

Claims (3)

[Claims] 1. An address conversion TLB access in an information processing system in which a logical address from a DMA (direct memory access) control unit is converted into a physical address by an address conversion TLB and a main memory is accessed by the physical address. A control method, wherein the storage means is provided separately from the main memory and stores a physical address corresponding to the logical address in advance; and the TLB for address conversion is searched by a logical address from the DMA control unit. A TLB access control method for address conversion, comprising: index means for generating a result; and access means for accessing the storage means when the index result indicates a mishit. 2. When the index result indicates a mishit,
2. The TLB access control method for address conversion according to claim 1, further comprising control means for controlling writing of a physical address obtained by accessing said storage means by said access means to said TLB for address conversion. 3. The address according to claim 1, wherein an access from the CPU to the main memory and an access from the DMA controller are controlled in parallel in the information processing system. T for conversion
LB access control method.