JPS6311799U - - Google Patents

Info

Publication number
JPS6311799U
JPS6311799U JP10300686U JP10300686U JPS6311799U JP S6311799 U JPS6311799 U JP S6311799U JP 10300686 U JP10300686 U JP 10300686U JP 10300686 U JP10300686 U JP 10300686U JP S6311799 U JPS6311799 U JP S6311799U
Authority
JP
Japan
Prior art keywords
circuit
signal
refresh circuit
access
access signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10300686U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10300686U priority Critical patent/JPS6311799U/ja
Publication of JPS6311799U publication Critical patent/JPS6311799U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のメモリリフレツシユ回路の一
実施例を示すブロツク図である。 1……リフレツシユ回路、2……選択回路、3
……制御回路、4……ダイナミツクRAM、5…
…CPU、S1,S2……アクセス信号、S3,
S5……アドレス信号、S4,S6……メモリ制
御信号。
FIG. 1 is a block diagram showing an embodiment of the memory refresh circuit of the present invention. 1... Refresh circuit, 2... Selection circuit, 3
...Control circuit, 4...Dynamic RAM, 5...
...CPU, S1, S2...Access signal, S3,
S5...Address signal, S4, S6...Memory control signal.

Claims (1)

【実用新案登録請求の範囲】 リフレツシユ回路と、 CPUからの第1のアクセス信号と一定の周期
で送出されるリフレツシユ回路からの第2のアク
セス信号のうちいずれが早く入力されたかにより
、早く入力された一方のアクセス信号を出力する
選択回路と、 前記第1または第2のいずれのアクセス信号が
入力されたかにより、CPUまたはリフレツシユ
回路から送出されたアドレス信号とメモリ制御信
号を入力して、CPUまたはリフレツシユ回路か
らダイナミツクRAMをアクセスするのに必要な
波形の信号を発生してダイナミツクRAMに出力
する制御回路を備えたメモリリフレツシユ回路。
[Claims for Utility Model Registration] The first access signal from the refresh circuit, the first access signal from the CPU, and the second access signal from the refresh circuit that are sent out at a constant cycle are input earlier depending on which one is input earlier. a selection circuit that outputs one of the access signals; and a selection circuit that inputs an address signal and a memory control signal sent from the CPU or a refresh circuit, depending on whether the first or second access signal is input, and A memory refresh circuit includes a control circuit that generates a waveform signal necessary for accessing a dynamic RAM from the refresh circuit and outputs it to the dynamic RAM.
JP10300686U 1986-07-03 1986-07-03 Pending JPS6311799U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10300686U JPS6311799U (en) 1986-07-03 1986-07-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10300686U JPS6311799U (en) 1986-07-03 1986-07-03

Publications (1)

Publication Number Publication Date
JPS6311799U true JPS6311799U (en) 1988-01-26

Family

ID=30975164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10300686U Pending JPS6311799U (en) 1986-07-03 1986-07-03

Country Status (1)

Country Link
JP (1) JPS6311799U (en)

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