JPH021923U - - Google Patents

Info

Publication number
JPH021923U
JPH021923U JP7999488U JP7999488U JPH021923U JP H021923 U JPH021923 U JP H021923U JP 7999488 U JP7999488 U JP 7999488U JP 7999488 U JP7999488 U JP 7999488U JP H021923 U JPH021923 U JP H021923U
Authority
JP
Japan
Prior art keywords
pulse width
pulse
generating means
winding
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7999488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7999488U priority Critical patent/JPH021923U/ja
Publication of JPH021923U publication Critical patent/JPH021923U/ja
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る絶縁クロツク回路の一実
施例を示す構成ブロツク図、第2図は第1図回路
の動作を示すタイムチヤート、第3図は従来の絶
縁クロツク回路の一例を示すブロツク図、第4図
は第3図回路の動作を示すタイムチヤートである
。 5……パルストランス、6……第2のパルス幅
発生手段、10……第1のパルス幅発生手段、C
i……パルス入力信号。
FIG. 1 is a configuration block diagram showing one embodiment of an insulated clock circuit according to the present invention, FIG. 2 is a time chart showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional insulated clock circuit. FIG. 4 is a time chart showing the operation of the circuit shown in FIG. 5... Pulse transformer, 6... Second pulse width generating means, 10... First pulse width generating means, C
i...Pulse input signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パルス入力信号に同期してデユーテイレシオの
小さいパルス幅を発生する第1のパルス幅発生手
段と、このパルス幅発生手段の出力がその1次巻
線に加えられるパルストランスと、このパルスト
ランスの2次巻線から出力される信号のパルス幅
を広げる第2のパルス幅発生手段とを備えたこと
を特徴とする絶縁クロツク回路。
A first pulse width generating means that generates a pulse width with a small duty ratio in synchronization with a pulse input signal, a pulse transformer to which the output of this pulse width generating means is applied to its primary winding, and a secondary winding of this pulse transformer. 1. An insulated clock circuit comprising: second pulse width generating means for widening the pulse width of a signal output from the winding.
JP7999488U 1988-06-16 1988-06-16 Pending JPH021923U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7999488U JPH021923U (en) 1988-06-16 1988-06-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7999488U JPH021923U (en) 1988-06-16 1988-06-16

Publications (1)

Publication Number Publication Date
JPH021923U true JPH021923U (en) 1990-01-09

Family

ID=31304841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7999488U Pending JPH021923U (en) 1988-06-16 1988-06-16

Country Status (1)

Country Link
JP (1) JPH021923U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373392A (en) * 2001-06-13 2002-12-26 Takamisawa Cybernetics Co Ltd Data conversion device and telemeter device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373392A (en) * 2001-06-13 2002-12-26 Takamisawa Cybernetics Co Ltd Data conversion device and telemeter device

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