JPS63167265U - - Google Patents
Info
- Publication number
- JPS63167265U JPS63167265U JP5924687U JP5924687U JPS63167265U JP S63167265 U JPS63167265 U JP S63167265U JP 5924687 U JP5924687 U JP 5924687U JP 5924687 U JP5924687 U JP 5924687U JP S63167265 U JPS63167265 U JP S63167265U
- Authority
- JP
- Japan
- Prior art keywords
- square wave
- circuit
- sampling
- output terminal
- triangular wave
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案に係わる周波数−電圧変換装置
の一実施例を示す回路図、第２図は変換の過程を
示すタイムチヤート、第３図は出力電圧と周波数
の関係を示す図である。
２……パルス発生回路（波形整形回路）、３…
…方形波発生回路（フリツプフロツプ）、４，５
……三角波発生回路、６，７……サンプリング回
路、８，９……サンプリング指令回路、１０……
ホールド回路。
FIG. 1 is a circuit diagram showing an embodiment of a frequency-voltage converter according to the present invention, FIG. 2 is a time chart showing the conversion process, and FIG. 3 is a diagram showing the relationship between output voltage and frequency. 2... Pulse generation circuit (waveform shaping circuit), 3...
...Square wave generation circuit (flip-flop), 4, 5
... Triangular wave generation circuit, 6, 7 ... Sampling circuit, 8, 9 ... Sampling command circuit, 10 ...
hold circuit.
Claims (1)
極性部に対応したパルスを発生するパルス発生回
路と、 (ロ) 上記パルス発生回路からのパルスの立ち上
がりまたは立ち下がり毎に、第１、第２の出力端
子の出力レベルを切り換えることにより、各出力
端子から方形波を交互に出力する方形波発生回路
と、 (ハ) 上記方形波発生回路の第１、第２の出力端
子からの各方形波を、所定の時定数で積分処理す
ることにより、三角波に変換する第１、第２の三
角波発生回路と、 (ニ) 上記方形波発生回路の第１出力端子の方形
波の立ち下がりまたは第２出力端子の方形波の立
ち上がりを検出して、サンプリング信号を発生す
る第１のサンプリング指令回路と、 (ホ) 上記方形波発生回路の第１出力端子の方形
波の立ち上がりまたは第２出力端子の方形波の立
ち下がりを検出して、サンプリング信号を発生す
る第２のサンプリング指令回路と、 (ヘ) 上記第１サンプリング指令回路からの信号
を受けて、第１三角波発生回路からの三角波の極
点電圧をサンプリングする第１のサンプリング回
路と、 (ト) 上記第２サンプリング指令回路からの信号
を受けて、第２三角波発生回路からの三角波の極
点電圧をサンプリングする第２のサンプリング回
路と、 (チ) 上記各サンプリング回路から交互に送られ
てくる三角波の極点電圧を保持するホールド回路 とを備えたことを特徴とする周波数−電圧変換装
置。[Scope of Claim for Utility Model Registration] (a) A pulse generation circuit that shapes one polarity of an AC signal and generates a pulse corresponding to this polarity, and (b) The rising edge of the pulse from the pulse generation circuit. or a square wave generation circuit that alternately outputs a square wave from each output terminal by switching the output level of the first and second output terminals at each falling edge; , first and second triangular wave generation circuits that convert each square wave from the second output terminal into a triangular wave by integrating with a predetermined time constant; (d) the first of the square wave generation circuits; (e) a first sampling command circuit that generates a sampling signal by detecting the falling edge of the square wave at the output terminal or the rising edge of the square wave at the second output terminal; (f) a second sampling command circuit that generates a sampling signal by detecting the rising edge of the square wave or the falling edge of the square wave at the second output terminal; (g) A first sampling circuit that samples the voltage at the extreme point of the triangular wave from the second triangular wave generation circuit; A frequency-voltage conversion device comprising: a second sampling circuit; and (h) a hold circuit that holds the pole voltage of the triangular wave alternately sent from each of the sampling circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5924687U JPS63167265U (en) | 1987-04-21 | 1987-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5924687U JPS63167265U (en) | 1987-04-21 | 1987-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63167265U true JPS63167265U (en) | 1988-10-31 |
Family
ID=30890561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5924687U Pending JPS63167265U (en) | 1987-04-21 | 1987-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63167265U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4314703Y1 (en) * | 1964-12-29 | 1968-06-20 |
-
1987
- 1987-04-21 JP JP5924687U patent/JPS63167265U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4314703Y1 (en) * | 1964-12-29 | 1968-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63167265U (en) | ||
| JPH01151439U (en) | ||
| JPS596334U (en) | Peak hold circuit | |
| JPS6242334U (en) | ||
| JPH02108439U (en) | ||
| JPS60158161U (en) | frequency/voltage converter | |
| JPS6188337U (en) | ||
| JPH0312528U (en) | ||
| JPS63117115U (en) | ||
| JPS62134076U (en) | ||
| JPS63105880U (en) | ||
| JPS6152870U (en) | ||
| JPH0348925U (en) | ||
| JPS61174225U (en) | ||
| JPS6454428U (en) | ||
| JPS6399417U (en) | ||
| JPS61116436U (en) | ||
| JPS61128699U (en) | ||
| JPS62103325U (en) | ||
| JPS5888448U (en) | analog to digital converter | |
| JPS6340900U (en) | ||
| JPS6372936U (en) | ||
| JPS5860261U (en) | Process analyzer | |
| JPS6381517U (en) | ||
| JPS647474U (en) |