JPS5888448U

JPS5888448U - analog to digital converter

Info

Publication number: JPS5888448U
Application number: JP14777782U
Authority: JP
Inventors: 貞夫山本
Original assignee: 横河電機株式会社
Priority date: 1982-09-29
Filing date: 1982-09-29
Publication date: 1983-06-15

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は本考案の変換器の一実施例を示すブロック図、
第２図は第１図の変換器の動作を説明するための波形図
、第３図及び第４図はそれぞれ本考案の別の実施例のブ
ロック図である。ＰＷＭ・・・パルス幅変調回路、ＥＣ・・・方形波電圧
発生器、ＩＧ・・・積分器、ｃｏｐ・・・比較器、＋Ｉ
５・・・基準電流源、ＤＩＧ・・・ディジタル変換回路
、ＣＯＵ。ＣＯＵ□・・・計数器、ＲＯＭ・・・リードオンリメモ
リ、ＭＵＬＴ・・・マルチプライヤ。FIG. 1 is a block diagram showing an embodiment of the converter of the present invention;
FIG. 2 is a waveform diagram for explaining the operation of the converter of FIG. 1, and FIGS. 3 and 4 are block diagrams of other embodiments of the present invention, respectively. PWM...pulse width modulation circuit, EC...square wave voltage generator, IG...integrator, cop...comparator, +I
5...Reference current source, DIG...Digital conversion circuit, COU. COU□...Counter, ROM...Read-only memory, MULT...Multiplier.

Claims

[Scope of utility model registration request]

(1) It has a comparator that adds and integrates the analog input, a square wave voltage with a period of T, and the output of a positive or negative reference power source using an integrator, and compares the integrator output with the reference voltage. a pulse width modulation circuit configured to switch the pair of references so that the summation input supplied to the integrator at the output of the pulse width modulation signal becomes substantially zero in one cycle of the pulse width modulation signal; A first counter that overflows by 1/27 of the period T, a read-only memory whose address is specified by the count value of the counter, and the output data of this read-only memory is given as its set value, and the input clock pulse is a multiplier for converting into a pulse signal with a frequency according to a set value; a period from when the first counter overflows to a rise or fall of the pulse width modulation signal obtained by the pulse width modulation circuit; an analog-to-digital converter comprising: a digital conversion circuit having means for providing a multiplier output to a counter;

(2) The analog-to-digital converter according to claim 1, wherein the first counter is used as a counter for addressing a read-only memory.

(3) A second counter separate from the first counter is provided as a counter for addressing the read-only memory, and the output of the multiplier is applied to this second counter via a frequency divider. An analog-to-digital converter according to claim (1) of the utility model registration.

(4) A practical method in which a second counter separate from the first counter is provided as a counter for address specification of read-only memory, and a clock pulse of a constant frequency is applied to this second counter. An analog-to-digital converter as set forth in claim (1) of patent registration.