JPS6048388U - Inverter gate signal generation circuit - Google Patents
Inverter gate signal generation circuitInfo
- Publication number
- JPS6048388U JPS6048388U JP13991883U JP13991883U JPS6048388U JP S6048388 U JPS6048388 U JP S6048388U JP 13991883 U JP13991883 U JP 13991883U JP 13991883 U JP13991883 U JP 13991883U JP S6048388 U JPS6048388 U JP S6048388U
- Authority
- JP
- Japan
- Prior art keywords
- gate signal
- generation circuit
- signal generation
- inverter gate
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示す全体構成図、第２図は
本考案におけるキャリア周波数特性を示す図、第３図は
第１図における加算器５とキャリア信号発生器６の一実
施例を示す回路図、第４図は第３図の要部波形図である
。
１・・・出力設定器、２・・・電圧−周波数変換器、３
・・・乗算器、４・・・固定バイアス設定器、５・・・
加算器、６・・・キャリア信号発生器、７・・・比較器
、８・・・論理ゲート回路、９・・・インバータ主回路
、１０・・・９＋ｔａ、６３・・・アナログスイッチ。FIG. 1 is an overall configuration diagram showing one embodiment of the present invention, FIG. 2 is a diagram showing carrier frequency characteristics in the present invention, and FIG. 3 is an implementation of the adder 5 and carrier signal generator 6 in FIG. 1. A circuit diagram showing an example, FIG. 4 is a waveform diagram of the main part of FIG. 3. 1... Output setting device, 2... Voltage-frequency converter, 3
... Multiplier, 4... Fixed bias setter, 5...
Adder, 6... Carrier signal generator, 7... Comparator, 8... Logic gate circuit, 9... Inverter main circuit, 10... 9+ta, 63... Analog switch.
Claims (1)
比較してパルス幅変調したゲート信号を発生するＰＷＭ
方式インバータのゲート信号発生回路において、上記イ
ンバータ出力周波数（電圧）信号にバイアス分を加算し
て上記キャリア信号の周波数を設定する手段を備えたこ
とを特徴とするインバータのゲート信号発生回路。PWM that generates a pulse width modulated gate signal by comparing the inverter output frequency (voltage) signal and carrier signal
A gate signal generation circuit for an inverter, characterized in that the gate signal generation circuit for an inverter comprises means for adding a bias amount to the inverter output frequency (voltage) signal to set the frequency of the carrier signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13991883U JPS6048388U (en) | 1983-09-09 | 1983-09-09 | Inverter gate signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13991883U JPS6048388U (en) | 1983-09-09 | 1983-09-09 | Inverter gate signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6048388U true JPS6048388U (en) | 1985-04-05 |
| JPH025675Y2 JPH025675Y2 (en) | 1990-02-09 |
Family
ID=30313449
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13991883U Granted JPS6048388U (en) | 1983-09-09 | 1983-09-09 | Inverter gate signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6048388U (en) |
-
1983
- 1983-09-09 JP JP13991883U patent/JPS6048388U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH025675Y2 (en) | 1990-02-09 |
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