JPH025675Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a gate signal generation circuit for a pulse width modulation (PWM) type inverter.

A PWM inverter uses a pulse train signal (pulse width modulation signal) obtained by switching an output frequency signal using a carrier wave (carrier) as a switching signal (gate signal) for the inverter main circuit. this
There are two types of PWM signal generation: a synchronous method that changes the carrier frequency in synchronization with the inverter output frequency, and an asynchronous method that does not synchronize the carrier frequency with the inverter output frequency. There are also synchronous and asynchronous methods that change the frequency ratio in stages. There are four methods:

(1) Keep the carrier frequency constant regardless of changes in the inverter output frequency (asynchronous type).

(2) The carrier frequency is switched in multiple stages according to changes in the inverter output frequency (asynchronous method).

(3) Create a carrier frequency by dividing the frequency at a fixed ratio from an oscillator that has the same frequency as the inverter output frequency (synchronous method).

(4) A carrier frequency is created by dividing the oscillator with the same frequency as the inverter output frequency, but the division ratio is switched to multiple stages depending on the inverter output frequency (synchronous type).

These systems have advantages and disadvantages, but those that switch the carrier frequency according to the inverter output frequency cause a discontinuous change in the inverter output at the switching point, and those that have an electric motor as a load cause a torque shock in the motor. Therefore, the methods described in item (1) or (3) above are adopted for inverters in which torque changes are a problem, but these methods also have the following problems.

In the method described in item (1) above, if the carrier frequency is fixed at a high value in consideration of noise countermeasures, etc., the operation speed of the main circuit switching element and the transmission delay in the gate signal generation circuit will increase the PWM pulse width in the low frequency region. The effect of the fixed portion of the current becomes large, and the waveform distortion of the output current becomes large, and in some cases, almost no current flows.

In addition, in the method in item (3), if an appropriate carrier frequency is selected in the low frequency range, the output frequency will be limited at high frequencies, and conversely, if an appropriate carrier frequency is selected in the high frequency range, the number of pulses will be limited in the low frequency range. The lower limit frequency is limited because the current ripple increases due to insufficient frequency.
This can be done by selecting the carrier frequency and output frequency ratio within a high digit range, but if the number of digits of the frequency divider becomes extremely large or the resolution of the frequency detection means limits this.

This invention was developed in view of the above-mentioned circumstances, and it is possible to continuously change the carrier frequency in response to changes in the inverter output frequency, and to obtain a PWM signal with an appropriate carrier frequency from low frequency to high frequency. The object of the present invention is to provide a gate signal generation circuit.

The present invention has a configuration in which the carrier frequency setting value is obtained by adding a fixed bias amount to the inverter output frequency setting value, and with a relatively simple circuit configuration, the carrier frequency does not become extremely low in the low frequency range and becomes extremely low in the high frequency range. It is characterized by the fact that it does not become too high.

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention. Inverter output setter 1 is the setting voltage
V _S is used as the output voltage and output frequency setting value to be the voltage input of the voltage-frequency converter (e.g., voltage controlled oscillator) 2, and is further input to one side of the multiplier 3, and is multiplied by the input of the output frequency ω of the converter 2. be done.
Multiplier 3 obtains an output frequency (voltage) signal (for example, a sine wave) v having a fixed ratio between the output frequency and output voltage of the inverter by controlling the amplitude of the signal of output frequency ω using a set voltage V _S .

On the other hand, the set value V _S of the output setter 1 is added to the bias set value V _B of the fixed bias setter 4.
The output of adder 5 for this addition is applied to carrier signal generator 6 as a frequency control signal. The signal generator 6 generates a carrier signal f having a frequency that is a constant ratio to the frequency control signal (=V _S +V _B ).
(for example, a triangular wave signal).

The comparator 7 obtains a PWM signal by comparing the levels of the output frequency (voltage) signal v and the carrier signal f. This PWM signal is divided and amplified into gate pulses by the logic gate circuit 8 for each phase, and turns on/off the switching elements of the inverter main circuit 9. 10 is an electric motor as an inverter load;
11 is an AC power source.

In this way, by setting the carrier frequency by adding the fixed bias amount V _B to the output frequency (voltage) set value V _S , the output voltage V has a constant ratio with respect to the inverter output frequency F, as shown in Figure 2. At the same time, it is possible to obtain a linear characteristic in which the carrier frequency f _C has a fixed bias component f _B when the output frequency F is zero, and increases in proportion to the rise in frequency F. The carrier frequency f _C enables an appropriate frequency setting with a low ratio (slope) in which the inverter output frequency is relatively high in the low frequency range and relatively low in the high frequency range. Further, the carrier frequency f _C can be continuously changed from a low frequency to a high frequency, and unlike conventional stepwise switching, no torque discontinuity point (torque shock) is generated in the electric motor 10.

Note that the characteristics of the carrier frequency f _C are not limited to being linear over the entire area as shown by the solid line in Figure 2, but are
It is also possible to set a bias that lowers only the low frequency range, as shown by the broken line f _C ' in the figure, to reduce waveform distortion in the low frequency range and achieve noise reduction characteristics.

FIG. 3 is a circuit diagram showing one embodiment of the adder 5 and carrier signal generator 6 in FIG.
This is the case when obtaining the carrier characteristic f _C shown in the figure. Adder 5 adds the set values V _S and V _B with negative polarity to obtain a positive output. The carrier signal generator 6 consists of 6 ₁ to _{6 4} , the inverting amplifier 6 ₁ inverts and amplifies the output of the adder 5 with a gain of 1, and the summing integrator 6 ₂ inverts the output of the adder _{5 .}
output and adder 5 through analog switch ₆₃
The output of The comparator ₆₄ compares the output of the summing integrator ₆₂ with hysteresis characteristics, and the hysteresis width is low resistance.
It is set by R ₁ and R ₂ , and the output controls the on/off of analog switch 6 ₃ . In the figure, A1 to A4 are operational amplifiers.

The main waveforms in this configuration are shown in FIG. During the ON period (T _ON ) of the analog switch ₆₃ , the input of the summing integrator ₆₂ becomes positive polarity relative to the output (positive polarity) of the adder 5, and its output falls with a negative slope. . Then, the output of the summing integrator ₆₂ is the reference level of the comparator ₆₄ .
When V _L is reached, the output of the comparator 6 ₄ is inverted to turn off the analog switch 6 ₃ and the reference level is switched from V _L to V _H. When the analog switch ₆₃ is turned off, the input of the summing integrator ₆₂ becomes negative during its off period (T _OFF ), and its output rises from the reference level V _L toward V _{H .}
When the output of the comparator ₆₄ is restored, the analog switch ₆₃ is turned on again. By repeating this process, the output of the summing integrator ₆₂ becomes a triangular wave as a carrier signal, and its frequency is the set value.
Determined by the sum of V _S and V _B.

As described above, according to the present invention, the carrier frequency is set by adding a fixed bias value to the inverter output frequency (voltage) setting value, so the carrier frequency is continuously changed from low frequency to high frequency and adjusted to an appropriate frequency. There are effects that can be set. Also,
In terms of configuration, it is a configuration that adds a means to add a fixed bias setter to the output frequency setting value, which is simpler than a system that changes the carrier frequency step by step according to the output frequency without sacrificing the characteristics of the asynchronous type. Can be configured.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram showing an embodiment of the present invention;
FIG. 2 is a diagram showing the carrier frequency characteristics of the present invention, FIG. 3 is a circuit diagram showing an embodiment of the adder 5 and carrier signal generator 6 in FIG. 1, and FIG. 4 is the main part of FIG. 3. FIG. 1... Output setting device, 2... Voltage-frequency converter, 3... Multiplier, 4... Fixed bias setting device,
5... Adder, 6... Carrier signal generator, 7...
... Comparator, 8 ... Logic gate circuit, 9 ... Inverter main circuit, 10 ... Electric motor, 6 ₃ ... Analog switch.

Claims (1)

[Scope of utility model registration request] In the gate signal generation circuit of a PWM inverter that compares the inverter output frequency (voltage) signal and the carrier signal to generate a pulse width modulated gate signal, the bias component is added to the inverter output frequency (voltage) signal and the An inverter gate signal generation circuit characterized by comprising means for setting the frequency of a carrier signal.