JPS6126316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for a variable frequency pulse width modulation inverter (hereinafter referred to as a PWM inverter) used to operate an AC motor at variable speed.

[Conventional technology]

Generally, the main circuit of a PWN inverter, as shown in Figure 1, includes a DC power supply 1, a power transistor 2,
It consists of a feedback diode 3. The pulse width modulation signal (square wave signal) applied to the base of the transistor 2 constituting the PWM inverter shown in FIG. 1 is obtained by comparing the modulated wave of the DC level signal with a carrier wave of a triangular wave or a sawtooth wave. on the other hand,
When driving an AC motor such as an induction motor with a PWM inverter, in order to keep the motor magnetic flux constant, the ratio of the inverter's output voltage V ₁ to frequency ₁ is V ₁ /
₁ is controlled constant. In addition, in the low frequency range, the number of pulses during a half cycle of the output voltage is increased in order to reduce harmonic components of the motor current, and as the frequency moves to the high frequency range, the number of pulses is decreased to increase the output voltage. ing.

FIG. 2 shows a waveform diagram when the number of pulses is switched in three stages.

Figure 2 shows three types of triangular waves X with different frequencies,
This is an example in which a pulse width modulation signal is obtained by comparing Y, Z and a DC level signal g. In Figure 2,
α, β, γ are each frequency domain, ,,
is the boundary frequency of In addition, the rectangular wave signals A, B, and C in Fig. 2 are the DC level signal g and the triangular wave X,
This is a pulse width modulation signal obtained by comparing Y and Z. Figure 3 shows the relationship between voltage and frequency when the number of pulses during a half cycle in the operating frequency range of Figure 2 is set to, for example, 9, 5, and 3, and V ₁ / ₁ is controlled to be constant. It becomes like being.

Conventionally, a control device as shown in FIG. 4 has been used to obtain pulse width modulated pulses as described above.

In FIG. 4, 100, 101, and 102 are triangular wave generation circuits that generate triangular waves X, Y, and Z, which are carrier waves according to the number of pulses to be changed; and 103
are operation pulse number region designation circuits, 104, 105,
A comparator 106 obtains a pulse width modulation signal by comparing the output signals of the oscillators 100, 101, and 102 with the DC level signal output from the PI regulator 111;
07 is a pulse number selection circuit for selecting the number of pulses, and 108 and 109 are interchangeable between pulse width modulation signals generated in each region so that arm short circuit does not occur even if the number of pulses is switched at any time. 110 is a three-phase reference synchronization generation circuit for synchronizing with the gate logic circuit; 110 is a pulse number switching signal generation circuit;
1,112 is a PI regulator.

In such a configuration, the triangular wave generation circuit 10
0, 101, and 102, in order to perform constant V ₁ / ₁ control, it is necessary to make the peak values of the three triangular waves X, Y, and Z equal and constant despite fluctuations in the frequency command.

[Problem that the invention seeks to solve]

In order to improve the drive characteristics of an AC motor, it is necessary to increase the number of pulse number switching stages. In the conventional device described above, if the number of pulse number switching stages is increased, the number of triangular wave generation circuits must be increased accordingly. The number of stages for switching the number of pulses is usually 10 or more, and it is necessary to synchronize the carrier wave and the inverter output voltage, which complicates the control device and increases the number of parts. Therefore, it has the disadvantage of high cost.

An object of the present invention is to reduce the number of parts of a control device and improve motor drive characteristics.
The purpose of the present invention is to provide a control device for a PWM inverter.

[Means for Solving the Problems] The present invention provides a plurality of 1/2-minute periods in which clock pulses having a frequency proportional to the frequency command of the inverter are connected in series, and a 1/2-minute period according to the frequency command of the inverter. The output of the period is selected and added to one carrier wave generation circuit, and a carrier wave signal having a constant peak value and a variable frequency is obtained from this one carrier wave generation circuit.

[Effect]

Since a carrier wave signal with a constant peak value and variable frequency is obtained from one carrier wave generation circuit, the configuration of the control device can be simplified even if the number of pulse number switching stages is large.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG.

The embodiment shown in FIG. 7 is an example in which a pulse width modulation signal is obtained by comparing a sawtooth wave signal and a DC level signal, but it can also be applied to a case where a combination of a triangular wave signal and a angular current level signal is used. FIG. 5 shows the line voltage waveform when the inverter is controlled by the pulse width modulation signal obtained by comparing the sawtooth wave signal and the DC level signal. 5a, b, and c show cases in which the number of pulses is 2 pulses, 4 pulses, and 8 pulses in a half cycle, respectively. The fundamental wave component obtained by expanding the above waveform into a Fourier series is approximately proportional to the pulse width ratio δ/Δ in the figure. By comparing the sawtooth signal and the DC level signal, V ₁ /
₁ , as shown in Figure 6A, when the magnitude of the DC level signal g (two levels g and g' are shown in the figure) changes from g' to g, The frequency of the sawtooth wave from ₁ to
All you have to do is change it to ₂ . In Figure 6, g is 2 of g'.
This shows the case where the value changes up to twice as much. As a result, ₁ is 2
Changes up to ₁ . As shown in Figure 6B and C, the sixth
A pulse width modulated signal shown by a broken line corresponding to ₁ in FIG. A and a modulated signal shown by a dotted line corresponding to ₂₁ in FIG. A are obtained. At this time, the period of the pulse width modulation signal △ ₁ ,
△ ₁ = ₂ △ _{2 , δ for △ 2 and conductivity δ 1 ,} δ ₂
There is a relationship: ₁ = δ ₂ . As a result, V ₁ / ₁ ^x δ ₁ /△ ₁ / ₁ = δ ₂ /△ ₂ /2
₁ , and V ₁ / ₁ can be kept constant.

Now, in Fig. 7, the maximum frequency setting value (V
The maximum frequency, for example, 60 Hz or 120 Hz, is selected by _F ) and applied to the acceleration time setting circuit 201. The acceleration time setting circuit 201 determines how long it will take to accelerate to the frequency setting value _VF . The acceleration time setting circuit 201 outputs an inverter frequency command f _R corresponding to the acceleration time. In order to perform V/f constant control, the voltage command of the inverter is changed in proportion to this frequency command. The frequency command signal output from the acceleration time setting circuit 201 is output from the voltage controlled oscillator 20.
2, are input to the pulse number determination circuit 206 and the DC level bias circuit 212, respectively. A 1/2 frequency divider 203 and a logic circuit 208 are connected to the voltage controlled oscillator 202, respectively. The square wave b whose frequency is divided by the 1/2 frequency divider 203 is further divided into the square wave c having a frequency of 1/2 by the 1/2 frequency divider 204, which is counted by the ring counter 205. . ring counter 205
The count values _d0 to _d5 are input to the logic circuit 215. On the other hand, the number of pulses determined by the pulse number determining circuit 206 (any one of p, q, or r shown in FIG. 9B) is output to the flip-flop circuit 207. The flip-flop circuit 207 is configured to receive output signals b and c from the 1/2 frequency dividers 203 and 204, and a signal f synchronized with the output signals of the 1/2 frequency dividers 203 and 204. It is input to logic circuit 208 . The logic circuit 208 includes a voltage controlled oscillator 202, a 1/2 frequency divider 203, 2
04 and the output signal f of the flip-flop circuit 207, and its output signal h is input to the monostable circuit 209. The output of the monostable circuit 209 (which has a frequency f _p , f q , or f _r corresponding to the number of pulses p, _q , and r of the pulse number determination circuit 206) is a level converter composed of an analog switch. It is input to circuit 210. In addition, the level conversion circuit 2
10 is the frequency command f of the acceleration time setting circuit 201.
_R is also added. The level conversion circuit 210 applies a signal j whose level is set according to the frequency command f _R to the sawtooth wave generation circuit 211 . Frequency command f
_R is input to the DC level bias circuit 212. The voltage detection signal is subtracted from the output signal (voltage command signal) of the DC level bias circuit 212,
The resulting signal is input to voltage control circuit 213. The sawtooth wave signal l generated by the sawtooth wave generation circuit 211 becomes one input of the comparator 214. A signal g' output from the voltage control circuit 213 is input to the comparator 214. logic circuit 21
The output signal m of the comparator 214 and the output signals d ₀ to d 5 of the hexadecimal ring counter 206 are input to ₅ .
Note that when voltage feedback is not taken, the signal output from the DC level bias circuit 212 is
becomes g′.

Next, the operation shown in FIG. 7 will be explained with reference to the time chart shown in FIG. 10.

It is now assumed that the frequency command f _R of the inverter is in a region where the number of pulses during a half cycle of the output voltage changes from a state of q (=8) to a state of r (=4).

The voltage controlled oscillator 202 outputs a square wave signal a with a conduction rate of 50%. The square wave signal a is successively divided in half by the 1/2 frequency dividers 203 and 204 to become square wave signals b and c, respectively. The final stage 1/2 frequency divider 204 is a hexadecimal ring counter 20
5, and the square wave signal c is input to the ring counter 205. Square waves _d0 to _d5 synchronized with the rising edge of the square wave signal c are detected by the ring counter 20.
Output from 5.

A case where the frequency command f _R of the inverter is in a region where the inverter is operated with the number of pulses q will be explained. A determination signal e for selecting the number q of pulses generated by the pulse number determination circuit 206 is input to the flip-flop circuit 207. The judgment signal e is taken in by the flip-flop circuit 207 in synchronization with the rise of the square wave signal b. Command signal f to select the number of pulses q
is output from the flip-flop circuit 207, the logic circuit 208 outputs square wave signals a, b, c.
Among them, square wave signal b is selected. As a result, a signal h is obtained. The above flip-flop circuit 207
and the logic circuit 208 selects the frequency division ratio. When the signal h enters the monostable circuit 209, the monostable circuit 209 outputs a differential pulse i and an inverted signal j of the differential pulse i in synchronization with the rising and falling points of the signal h. An example of the level conversion circuit 210 in which the inverted signal j is applied to the level conversion circuit 210 is shown in FIG. The inverted signal j is applied to the gate f _g of the level conversion circuit 210. The level conversion circuit 210 outputs an inverter frequency command f _R when the signal j is at a high level.
Take in (=g). The magnitude of the inverter frequency command f _R is converted by an operational amplifier 301 within the level conversion circuit 210 . The conversion gain is the square wave signal a,
It is determined to be inversely proportional to the period of b and c (for example, 1:2:4). Specifically, if the gain is 1 when square wave a is selected, it is 1/2 when square wave b is selected, and 1/2 when square wave c is selected.
4 and the gain is selected respectively. This is done in order to keep the peak value of the sawtooth wave l constant even if the period of the square wave changes. Thereby, V ₁ /F ₁ can be made constant by using a pulse width signal obtained from a comparison between a voltage command proportional to the inverter frequency command f _R and a sawtooth wave having a constant peak value.

The values selected as described above are input to the sawtooth wave generation circuit 211. Sawtooth wave generation circuit 21
1 consists of an integrator, and this value is the value of the signal j.
It is integrated during the high level period, and the output value of the integrator is reset for every differential pulse i. As a result, a sawtooth wave l is obtained.

On the other hand, the voltage command is the inverter frequency command f _R
A DC level signal g' (=g+Δg) obtained by adding a DC bias Δg shown in FIG. 9A by the DC level bias circuit 212 to (=g) is used. The reason for biasing by Δg is to prevent the gap magnetic flux from decreasing due to the voltage drop due to the primary resistance in the low speed range, thereby preventing the torque from decreasing. In FIG. 7, when performing voltage feedback, a voltage control system 213 shown by a dotted line is included, but if this is not present, a voltage command obtained from a DC level bias circuit 212 is input to one terminal of a comparator 214. A sawtooth wave l is input to the other terminal of the comparator 214. As a result, the DC level signal
The levels of g' and the sawtooth wave l are compared by a comparator 214 to obtain a pulse width modulated signal m.

The pulse width modulation signal m is logically connected to the output signals d ₀ to _{d 5} of the ring counter 205 in the logic circuit 215, and is converted into U-phase, V-phase, and W-phase gate signals _EU , _EV , and E.
_W is obtained. For example, the gate signal _EU is obtained by the following equation.

E _U = (d ₀ + d ₁・m + d ₂ ) + (d ₃ + d ₄ + d ₅ ) (d ₄・) ... (1) Gate signals obtained in this way E _U , _EV ,
E _W is applied to the gate of each upper arm of the inverter shown in Fig. 1, and inverted gate signals _U , _V ,
_W is applied to the gate of each lower arm, respectively. Note that the gate signal _U is not a completely inverted signal of _EU , and a dead time is provided in the gate signal _U so that the upper arm and the lower arm are not fired at the same time.

When the gate signal as described above is applied, a waveform as shown in FIG. 14 appears in the line voltage, for example, the line voltage E _UV of the UV phase.

Next, if the frequency command f _R of the inverter increases and the number of operating pulses changes to r (=4) at point A, then the number of pulses r is determined by the pulse number determination circuit 206.
A determination command e for selecting (=4) is output. For the determination command e, a flip-flop circuit 217 generates a command signal f synchronized with the square wave c. Command signal f
Accordingly, the square wave c is selected by the logic circuit 208 from time point B shown in FIG.

Monostable circuit 2 in the same way as in the case of pulse number q
At 09, signals i and j after time B are obtained. After time B, the period of the square wave c becomes twice as long as the period of the square wave b, so the integration time also becomes twice as long. Therefore, in order to keep the peak value of the sawtooth wave constant, the level conversion circuit 210 inputs the DC level k to the integrator.
is converted to 1/2. As a result, a sawtooth wave l with twice the period and a constant peak value is generated by the sawtooth wave generation circuit 21.
Obtained from 1. From now on, the gate signals _EU , _EV ,
Obtaining E _W is the same as obtaining the number of pulses q, so the explanation will be omitted. As shown in FIG. 10, the line voltage E _UV has a waveform of four pulses per half cycle.

Pulse width modulation control is performed as described above, and even if the number of pulse number switching stages increases, V ₁ / ₁ can be controlled to be constant by one carrier wave generator 202. Also, like the conventional circuit, f
Since a synchronous circuit is not used when the frequency is controlled to be constant, according to this embodiment, the range where variable frequency can be driven is expanded. Furthermore, according to this embodiment, the number of component parts is reduced compared to the conventional one, so the cost of the control circuit is reduced and the reliability is improved.

〔Effect of the invention〕

As described above, according to the present invention, a carrier wave signal having a constant amplitude value and a variable frequency can be obtained using one carrier wave generator, so that the number of parts of the control circuit can be reduced and costs can be reduced.

[Brief explanation of the drawing]

Figure 1 is the main circuit diagram of a pulse width modulation inverter.
Figure 2 is a diagram showing a pulse width modulation signal obtained by comparing a triangular wave with three types of frequencies and a DC level, and Figure 3 is a diagram showing a pulse width modulation signal obtained by comparing a triangular wave with three types of frequencies and a DC level.
= A diagram showing the relationship between the inverter output voltage (line voltage) and frequency when constant control is performed. Figure 4 is a control circuit diagram of a conventional PWM inverter. Figure 5 is a comparison configuration with a sawtooth wave DC level. Figure 6 is a diagram explaining the method of controlling V ₁ / ₁ = constant. Figure 7 is a diagram of the control circuit configuration of the PWM inverter when the above method is adopted. 8 is a circuit diagram of the switch level conversion circuit 210 in FIG. 7, FIG. 9 is a circuit diagram and compensation characteristic diagram of the DC level bias circuit 212 in FIG. 7,
FIG. 10 is a time chart explaining the operation of the embodiment shown in FIG. 201... Acceleration time setting circuit, 202... Voltage controlled oscillator, 203, 204... 1/2 frequency divider, 20
5... Ring counter, 206... Pulse number determination circuit, 209... Monostable circuit, 210... Level conversion circuit, 211... Sawtooth wave generation circuit, 212... DC level bias circuit, 214... Comparator, 215... Logic circuit.

Claims (1)

[Claims] 1. An oscillator that generates a square wave with a frequency proportional to the frequency command of the inverter, and a determination of the number of pulse width modulated pulses 2n (an integer of n1) that enters in a half cycle of the inverter output voltage based on the magnitude of the frequency command. A pulse number determining means, (n-1) 1/2 frequency dividers connected in series so as to sequentially divide the square wave output from the oscillator into 1/2, and a determination by the pulse number determining means. The number of pulse width modulation pulses is set to 2p (an integer of pn) by the command.
When commanded, the frequency is divided by 1/2 (p-1) from the (p-1)th connected 1/2 divider among the (n-1) 1/2 dividers. 1/2(p-
1) a frequency division ratio selection means for selecting a frequency-divided signal; a sawtooth wave generation circuit that integrates the 1/2 (p-1) frequency-divided signal to generate a sawtooth wave signal; and the inverter. and a voltage command means for generating a voltage command signal having a magnitude corresponding to the frequency command of the pulse width modulation, wherein the sawtooth wave signal and the voltage command signal are compared to obtain a pulse width modulation signal. Inverter control device.