JPS6074972A - Reference signal forming circuit of synchronous pwm inverter - Google Patents

Abstract

PURPOSE:To simply and inexpensively form a construction of a reference signal forming circuit of a synchronous PWM inverter by forming a reference signal of a PWM inverter with a purely digital construction using a programmable divider and a PLL circuit. CONSTITUTION:Dividing frequency of programmable dividers 10, 20, 30 40 are controlled by a microcomputer 100. A PLL circuit 50 has the dividers 30, 40 in its feedback circuit, and operates as a frequency multiplier. A reference clock of a microcomputer 100 is applied to the divider 10 to generate an inverter frequency reference. This inverter frequency reference is applied to the PLL circuit 50, the output of the circuit 50 is divided in frequency to obtain a PWM reference signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a circuit that digitally generates a reference signal for a PWM inverter.

[Prior Art] The ignition pulse of a synchronous PWM inverter, for example, an inverter whose switching element is a gate turn-off signal, is generated by comparing a reference triangular wave signal Vc and a sine wave signal ■cs, as shown in FIG. Vp indicates the output pulse.

In the case of a synchronous type, - the output pulse V included in the period
The number of pulses N of p is always an integer number, but since there is a limit to the switching frequency of the switching elements of the inverter,
As the output frequency fo of the inverter increases, the number N of pulses needs to be reduced accordingly. ? ffJ, it is necessary to prevent the modulation reference frequency=foXN from exceeding the maximum switching frequency fmtl-. However, when the inverter load is an AC motor, in order to reduce the torque pulsation of the motor, it is better to set the value of foXN as large as possible. However, as a result,
The modulation reference frequency f changes discontinuously as shown.

For this reason, in a conventional PWM control circuit using a microcomputer, as shown in FIG. After the signal is converted into an analog signal by a D/A converter 2, it is guided to a voltage/frequency converter 3 to obtain a PWM reference signal having a modulation reference frequency.

As described above, the conventional computer-controlled PWM reference signal generation circuit has the disadvantage that the circuit is complicated and expensive because it is necessary to convert the digital output of the ROM corresponding to the modulation reference frequency into an analog signal.

[Summary of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks of the prior art and provides a P L 1. , using a circuit to generate an inverter frequency reference by applying a reference clock of a microcomputer to the first programmable divider, and to generate an inverter frequency reference for each inverter frequency reference.
By dividing the output of the PLL circuit using the second programmable divider described above to obtain the PWM reference signal, the PWM reference signal can be obtained purely digitally.
This invention proposes a reference signal generation circuit for a synchronous PWM inverter that can generate M reference signals and is therefore cheaper than conventional ones.

[Embodiments of the invention]

FIG. 4 is a block diagram showing an embodiment of the invention.

In the figure, 10, 20, 30, and 40 are programmable dividers (hereinafter abbreviated as frequency dividers), and the frequency division number thereof is controlled by the microcomputer 100. 50 is a PLL circuit, which connects the frequency dividers 30 and 40.
is included in its feedback circuit to perform a frequency doubler action.

The frequency divider 10 has a microcomputer +00 base ((1
A clock is input. The frequency divider 10 divides the frequency fc of the reference clock into a value corresponding to the output frequency fo of the inverter. In this case, if the frequency division number M1 of the frequency divider 10 is made sufficiently large, a highly accurate output frequency can be obtained. The output frequency thus obtained [0 is I) is given as the frequency base γ (to) of the L T-circuit 50. The output of the PI, L circuit 50 is input to the frequency divider (frequency division number M2) 20. .

Note that the frequency dividers 30 and 40 of the feedback circuit may be combined into a fixed divider.

Now, for the convenience of explanation, the frequency division number M3 of the -1 frequency divider 30 = 256
, if the frequency division number MIl of the frequency divider 40 is 135, then P
Due to the nature of the L L circuit 50, the output point 5I, 31.41
The frequencies appearing in are 256×135Xfo and 13, respectively.
5Xfo, fo, and the output of the PI-1 circuit 50 has a value corresponding to the output frequency fo. This value, i.e. 256
X135Xfo is applied to frequency divider 40. Therefore, the frequency division number M4 of the frequency divider 40 is set to, for example, 45.27.15.
...and the computer control deviation is the number of pulses N=3.5.
A PWM reference signal of a modulation frequency for 9... can be easily obtained with high accuracy.

〔Effect of the invention〕

As explained above, this invention has a purely digital configuration using a programmable divider and a PLL circuit, so it has the advantage that it can be constructed at a lower cost and simpler than the conventional one. .

[Brief explanation of the drawing]

Figure 1 is a waveform diagram of a synchronous PWM signal, Figure 2 is a diagram showing the relationship between the modulation reference frequency and the inverter output frequency,
Figure 3 is a block diagram of a conventional PWM reference signal generation circuit.
FIG. 4L:1 is a block diagram of an embodiment of the present invention. In the figure, 10 to 40 are programmable dividers, 5
Q, -PL 1-circuit, 100-microcomputer. Agent Masuo Oiwa Figure 3 Figure 4 Figure 00

Claims (1)

[Claims] (1) First and second programmable dividers controlled by a microcomputer, and a PLL circuit having a fixed or programmable divider in a feedback circuit and providing an output to the second programmable divider, The first programmable divider divides the frequency of the reference clock of the microcomputer to the inverter output frequency and applies it to the PLL circuit, controls the frequency division number of the second programmable divider, and controls the frequency of the second programmable divider.
Synchronous type 2w characterized by generating an M reference signal
Reference signal generation circuit for M inverter.