JPS62171314A - Pulse train signal generating circuit - Google Patents

Abstract

PURPOSE:To improve the accuracy of digital control by counting the 2nd clock pulse which are not frequency-divided by the 2nd counter until the output of the 1st counter coincides with a digital control signal and inputting the output signal of the 2nd counter to a rate multiplier instead of the digital control signal. CONSTITUTION:The 2nd counter 27 counts the 2nd clock pulses repeatedly every time a coincidence detection signal is inputted to the 2nd counter control circuit 26 from a comparator 25. Therefore, its output is N times as large as a digital control signal outputted from a digital setter 11. The rate multiplier 13 converts the frequency of the 1st clock pulses to generate and output a pulse train signal of frequency reduce in proportion to the 2nd counter output signal. At this time, the signal from the 2nd counter 27 is N times as large as the digital control signal, so the frequency of said pulse train signal is high correspondingly. This pulse train signal of high frequency is frequency-divided by a frequency divider 14 to a proper value and then inputted as a digital control signal to a digital control circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a circuit that generates a pulse train signal with a frequency proportional to a digital control signal.

[Prior art and its problems]

By using a control device that uses digital signals, the response speed and control accuracy of controlled equipment can be significantly improved compared to analog control devices. For example, by digitally controlling an inverter that outputs alternating current of variable voltage and variable frequency using pulse width modulation control, an alternating current motor driven by this inverter can be controlled with high precision. Incidentally, the control signal input to such a digital control device of an inverter is often input as a pulse train signal having a frequency corresponding to the level of the control signal.

FIG. 2 is a block diagram showing a conventional example of a pulse train signal generation circuit that is input to a digitally controlled inverter. In this FIG. It is converted to AC power and becomes an AC type! ! The digital controller 5 controls the transistor inverter 3 to change the frequency and voltage of the output AC power, thereby operating the AC motor 4 at a desired speed. The actual or set values of the speed, voltage, or current of the AC motor 4 are input to the digital control device 5 in the form of a pulse train signal, and this pulse train signal is formed as follows.

Reference numeral 11 denotes a digital setting device, in which, for example, the target operating speed of the AC motor 4 is set as a digital value.

The rate multiplier 13 combines the first clock pulse output from the first clock oscillator 12 and the digital setter 11.
The pulse train output from this rate multiplier 13 converts the frequency of the first clock pulse into a pulse train signal with a frequency reduced in proportion to the digital control signal. After the signal is appropriately frequency-divided by the frequency divider 14, it is input to the digital control device 5 described above.

By the way, in the configuration of the conventional example circuit shown in FIG. 2, the frequency of the pulse train signal input to the digital control device 5 is significantly reduced compared to the frequency of the first clock pulse. This invention has the disadvantage that control accuracy deteriorates and errors increase because the resolution per unit decreases. [Object of the Invention] This invention aims to reduce the frequency of a pulse train signal as a control signal input to a digital control device by reducing the frequency of a clock pulse as much as possible. It is an object of the present invention to provide a pulse train signal generating circuit that can maintain high control accuracy by setting the frequency to a high value close to the frequency of .

[Key points of the invention]

This invention provides a second clock output from a second clock oscillator.
The pulse train obtained by dividing the clock pulse into l/N using a frequency divider is input to the first counter and counted.
A comparator detects a match between the counter output and a preset digital control signal, and a second counter counts the undivided second clock pulse mentioned above until the controller detects a match. death,
If the output of this second counter is input to the rate multiplier instead of the digital control signal, since the output of this second counter is N times the digital control signal,
The frequency of the pulse train signal output from this rate multiplier is higher than that of the conventional one. Therefore, by inputting this into a digital finger control device, it is attempted to improve control accuracy.

[Embodiments of the invention]

FIG. 1 is a block diagram showing an embodiment of the present invention, and the content of the present invention will be explained below with reference to FIG.

In FIG. 1, the second clock pulse output from the second clock oscillator 2175 is inputted to the frequency divider 222, where its frequency is divided by 1/N, and then the first counter control circuit 23 and is input to the first counter 24,
Here, the second clock pulse frequency-divided by 1/N is counted, and its output is given to the comparator 25. On the other hand, since the digital control signal set by the digital setting device 11 is also given to the comparator 25, the first coincidence detection signal is output from the comparator 25 when the two human forces match.
It is output to the counter control circuit 23 and the second counter control circuit 26. Therefore, each time the coincidence detection signal is input to the first counter control circuit 23, the first counter 24 repeats counting of the second clock pulse whose frequency is divided by 1/N.

On the other hand, the undivided second clock pulse is input to the second counter 27 via the second counter control circuit 26 and is counted. Since counting of the second clock pulse is repeated each time the second clock pulse is input to the two-counter control circuit 26, the output of the second counter 27 will eventually be the digital control signal output from the digital setting device 11 multiplied by N.

The rate multiplier 13 inputs the first clock pulse output from the first clock oscillator 12 and the output signal from the second counter 27 described above, and makes the frequency of the first clock pulse proportional to the second counter output signal. It converts it into a pulse train signal with a reduced frequency and outputs it.
Since the signal from the second counter 27 is N times the digital control signal, this rate multiplier 13
Correspondingly, the frequency of the pulse train signal output by the controller also becomes a high value. This high frequency pulse train signal is sent to the branching unit 14.
After dividing the frequency into an appropriate value, it is input to the digital control circuit 5 as a digital control signal.

Note that this digital control device 5Fi, for example, the second
Like the conventional example shown in the figure, the transistor inverter 3 is digitally controlled, but the DC power supply 2, transistor inverter 3, and AC motor 4 are not shown in Figure 1.C [Effects of the Invention] This invention According to the method, a pulse train obtained by dividing the second clock pulse by 1//N is counted by a first counter,
During the period until the output of the first counter and the digital control signal match, a second counter counts the undivided second clock pulses, and uses the second counter output signal as a rate multiplier instead of the digital control signal. By inputting the pulse train signal to the rate multiplier, the frequency of the pulse train signal output from the rate multiplier is set to the highest possible value and the first
Having the frequency close to that of the clock pulse has the advantage that the accuracy of digital control can be easily improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.
The figure is a block diagram showing a conventional example of a generating circuit for a pulse train signal input to a digitally controlled inverter. 2...DC power supply, 3...Transistor inverter, 4...AC motor, 5...
・Digital control device, 11...Digital setting device, 12...First clock oscillator, 13...
...Rate multigrayer, 14... Frequency divider,
21...Second clock oscillator, 22...
・Frequency divider, 23...First counter control circuit, 2
4...First counter, 25...Comparator, 26...Second counter control circuit, 27
・・・・・・Second Callan Figure 1

Claims (1)

[Claims] 1) Input a clock oscillator, a clock pulse output from this clock oscillator, and a preset digital control signal, and convert the frequency of this clock pulse into a pulse train signal with a frequency reduced in proportion to the digital control signal. In a pulse train signal generation circuit configured with a rate multiplier for conversion, a second clock oscillator that outputs a second clock pulse, a frequency divider that divides the frequency of this second clock pulse, and a frequency-divided second clock pulse. a first counter that counts two clock pulses; a comparator that detects a match between the output signal of the first counter and the digital control signal; and a comparator that detects a match between the output signal of the first counter and the digital control signal; A pulse train signal generating circuit comprising: a second counter that counts a period until a detection signal is output and inputs the output signal to the rate multiplier instead of the digital control signal.