JPS58107624U - Pulse duty cycle variable circuit - Google Patents
Pulse duty cycle variable circuitInfo
- Publication number
- JPS58107624U JPS58107624U JP129182U JP129182U JPS58107624U JP S58107624 U JPS58107624 U JP S58107624U JP 129182 U JP129182 U JP 129182U JP 129182 U JP129182 U JP 129182U JP S58107624 U JPS58107624 U JP S58107624U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- duty cycle
- level converter
- pulse duty
- variable circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Pulse Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例によるパル又後縁遅延回路、第２図は本
考案の実施例による回路図、第３図はこの回路の゛パル
スタイミングチャート、第４図は本考案の他の実施例に
よる回路図、第５図はこの回路のタイミングチャートで
ある。
２．７二レベルコンバータ、３，４：）ランジスタ、６
：コンデンサ、８：論理演算素子。Fig. 1 is a conventional pulse or trailing edge delay circuit, Fig. 2 is a circuit diagram of an embodiment of the present invention, Fig. 3 is a pulse timing chart of this circuit, and Fig. 4 is another embodiment of the present invention. FIG. 5 is a timing chart of this circuit. 2.7 two-level converter, 3, 4:) transistor, 6
: Capacitor, 8: Logical operation element.
Claims (1)
、このレベルコンバータの出力パルスによって動作する
スイッチングトランジスタと、このスイッチングトラン
ジスタのコレクタに接続するコンデンサと、このコンデ
ンサを充電する定電流用トランジスタと、前記コンデン
サの端子電圧によって動作する第２のレベルコンバータ
と、このレベルコンバータの出力パルス及び前記入力パ
ルスとにより所望のパルス波形を得るための論理演算素
子とで構成したことを特徴とするパルスデューティ・サ
イクル可変回路。、A first level converter operated by a large power pulse, a switching transistor operated by an output pulse of this level converter, a capacitor connected to the collector of this switching transistor, a constant current transistor for charging this capacitor, A variable pulse duty cycle circuit comprising a second level converter operated by a terminal voltage, and a logic operation element for obtaining a desired pulse waveform from the output pulse of the level converter and the input pulse. . ,
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP129182U JPS58107624U (en) | 1982-01-11 | 1982-01-11 | Pulse duty cycle variable circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP129182U JPS58107624U (en) | 1982-01-11 | 1982-01-11 | Pulse duty cycle variable circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58107624U true JPS58107624U (en) | 1983-07-22 |
Family
ID=30014317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP129182U Pending JPS58107624U (en) | 1982-01-11 | 1982-01-11 | Pulse duty cycle variable circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58107624U (en) |
-
1982
- 1982-01-11 JP JP129182U patent/JPS58107624U/en active Pending
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