JPS63105880U - - Google Patents
Info
- Publication number
- JPS63105880U JPS63105880U JP20414186U JP20414186U JPS63105880U JP S63105880 U JPS63105880 U JP S63105880U JP 20414186 U JP20414186 U JP 20414186U JP 20414186 U JP20414186 U JP 20414186U JP S63105880 U JPS63105880 U JP S63105880U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal generating
- reset
- differentiating
- inverted signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000630 rising effect Effects 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
Landscapes
- Control Of Velocity Or Acceleration (AREA)
Description
第１図は本考案の一実施例を示す電気回路図、
第２図は第１図における信号波形図、第３図は従
来例を示す電気回路図、第４図は第３図における
信号波形図である。
１……微分回路、２……反転信号発生回路、３
……リセツト信号発生回路、４……積分回路、６
……ホールド回路。
FIG. 1 is an electrical circuit diagram showing an embodiment of the present invention;
2 is a signal waveform diagram in FIG. 1, FIG. 3 is an electric circuit diagram showing a conventional example, and FIG. 4 is a signal waveform diagram in FIG. 3. 1...Differential circuit, 2...Inverted signal generation circuit, 3
...Reset signal generation circuit, 4...Integrator circuit, 6
...Hold circuit.
Claims (1)
立上がりを検出する微分回路と、該微分回路の反
転信号を形成する反転信号発生回路と、この反転
信号の立上がりに同期するリセツト信号発生回路
と、前記微分回路の出力を積分し、リセツト信号
発生回路の出力によりリセツトされる積分回路と
、この積分回路の積分結果をホールドするサンプ
ルホールド回路とからなることを特徴とする周波
数―電圧変換回路。 a differentiating circuit that detects the rising edge of an input signal having a pulse width corresponding to the rotation speed; an inverted signal generating circuit that forms an inverted signal of the differentiating circuit; a reset signal generating circuit that synchronizes with the rising edge of the inverted signal; A frequency-voltage conversion circuit comprising: an integrating circuit that integrates the output of the differentiating circuit and is reset by the output of the reset signal generating circuit; and a sample-hold circuit that holds the integration result of the integrating circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20414186U JPS63105880U (en) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20414186U JPS63105880U (en) | 1986-12-26 | 1986-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63105880U true JPS63105880U (en) | 1988-07-08 |
Family
ID=31170120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20414186U Pending JPS63105880U (en) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63105880U (en) |
-
1986
- 1986-12-26 JP JP20414186U patent/JPS63105880U/ja active Pending