JPS5919456A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a PLL, by controlling a VCO with the result of direct phase comparison between an input signal and a regnerated clock with two D-FFs and two EORs. CONSTITUTION:D-FFs 9, 11 and EORs 10, 12 form a phase comparison means which detects the phase difference between an input signal (a) and a pi phase output (f) and where an output changes linearly against a change of phase difference over -pi to pi. This phase comparison means forms the PLL with an LPF 14, a VCO 15 and a frequncy divider 16, and a pi phase output (f) is outputted as a demodulation regenerating clock with coincident timing of a rise edge of the pi phase output (f), a rise edge of the input signal (a) and a fall edge. Further, an output (e) of the EOR 10 is a pulse having a pulse width in response to the phase difference between the rise and fall edges of the input signal (a) and the rise edge of the pi phase output (f). An output (d) of the EOR 12 has a pulse width equal to that of the O phase output (g) and the pi phase output (f).

Description

[Detailed description of the invention]

The present invention relates to a clock recovery circuit, and more particularly to a clock recovery circuit for demodulating a modulated signal using a run-length limited modulation method. The so-called run-length limited modulation method, which allows for self-clocking, has been adopted as a modulation processing method when transmitting digital information signals such as PCM (pulse code modulation) signals to recording media or transmission media, in consideration of higher density. There is. In this run-length limited modulation method, a demodulation clock signal is usually reproduced from a signal obtained from a recording medium or a transmission medium during demodulation. FIG. 1 is a block diagram showing a conventional example of a clock regeneration circuit that regenerates a clock signal. In the figure, an input signal consisting of a modulated signal based on a run-length limited modulation method reproduced from a recording medium such as a digital audio disk is supplied to a differentiating circuit 1 and a storage circuit 2 consisting of a D-type flip-flop or the like. Each time a rising edge and a falling edge of the input signal arrive from the differentiating circuit 1, a positive pulse and a negative pulse are outputted and supplied to the double-wave rectifier circuit 3. By inverting the polarity of the negative pulse output from the differentiating circuit 1 in the double-wave rectifier circuit 3, a positive pulse is obtained every time a 9-1 edge and a falling edge of the input signal arrive. Double wave rectifier circuit 3
The output of is supplied to the trigger input terminal of a monostable multivibrator (hereinafter abbreviated as monostable multi) 4. The inversion time of the monostable multi-1 is set to a time approximately equal to 1/2 of the period of 19 ruby regenerations. For example, the Q output of this skewer stabilizing multi 4 is supplied to a phase comparator circuit 5. The phase comparator 5 includes an LPF (low-pass filter) 6 and a VCO (voltage-controlled oscillator) 7.
L l-, (Please l-ocked L
001) ) is formed. Su (2w), V CO
The output of 1 is compared with the output of 4 in the phase comparator; It becomes the control power 11 of CO7. The output of VCO 7 is sent to differentiator circuit 1, double wave rectifier circuit 3 and Ill stabilization circuit 4.

[)@] is phase-corrected by the phase adjustment circuit 8 which compensates for the phase delay due to the delay time, and then supplied as a demodulation reproduction clock to a demodulation circuit (not shown) and also to the storage circuit 2 [
Not supplied to the I-tock input terminal. In the storage circuit 2, the -C input signal is latched (stored) by the reproduced clock, and a signal obtained by delaying the input signal by a half clock of the reproduced clock is output and supplied to the demodulation circuit (not shown). The conventional clock regeneration circuit as described above has a complicated configuration and requires a capacitor and a resistor for setting a time limit that determines the inversion time of the monostable multi-4. External attachment of the setting content 4J and the like required terminals, which had the disadvantage of not being suitable for IC implementation. It is therefore an object of the present invention to provide a clock regeneration circuit which is simple in construction, does not require external terminals such as time limit setting terminals, and is suitable for IC implementation. The clock reproducing circuit 41 according to the present invention is capable of combining an input signal with a signal according to the storage contents of the first storage means that temporarily stores the state of the input signal in synchronization with the pulse output from the pulse generation means. The pulse width of the signal obtained by taking the logical sum,
IJ+ between the output of the first storage means and the second storage means for temporarily storing the state of the output of the first storage means in synchronization with the pulse;
The repetition frequency of the pulse is controlled so that the pulse width of the signal obtained by the alistic OR is equal to each other.O1l? By doing this, the pulse is reproduced, racked, and output while eliminating the phase difference between the input signal and the pulse. Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 6. In FIG. 2, an input signal a consisting of a modulated signal based on a run-length limited modulation type is input to the D input terminal of a D-type flip-flop 9 serving as a first storage means and to one input terminal of exclusive OR groups 1 to 10. Supplied. [)
The 0 output of the flip-flop 9 is supplied to the D input terminal of a D-type flip-flop 11 serving as a second storage means, and the other input terminal of the exclusive OR gate h10 and the exclusive OR It is supplied to the -h input terminal of gate 12. The Q output C of the D-type flip-flop 11 is supplied to the other input terminal of the gate 12. Output of 12 to Goo 1 (1 is supplied to the 1-phase input terminal of operational amplifier 13 via resistor R+. Operational amplifier 13
A capacitor CI is connected between the 11-phase input terminal and ground. Furthermore, the output e of the gate 10 is supplied to the negative phase input terminal of the operational amplifier 13 via a resistor R2.
A =1 capacitor C7 is connected between the negative phase input terminal and the output terminal of the operational amplifier 13. These amplifiers 13,
] An LPF 14 is formed which extracts and outputs a low frequency component of a signal obtained by amplifying the difference between two inputs using capacitors C1 and C2 and resistors R+ and R2.
A control voltage is supplied from V C01b to V C01b. The output of the VCO 15 is divided into two by a frequency divider 16. Then, when the π-phase output of the frequency divider 16 is supplied to the clock of the D-type flip-flop 11, the demodulation regeneration signal is
The signal is supplied as one signal to a demodulation circuit (not shown). Also,
The O-phase output 9 of the frequency divider 16 is supplied to the clock input terminal of the 1) 6-type flip-flop 70, and the input signal Qa is latched to the D-type flip-flop 9.
A signal is outputted from the flip-flop 9 by delaying the input signal a by one half of the reproduced clock, and is supplied as data output to the demodulation circuit (not shown). The operation of each part in the above configuration will be explained with reference to FIGS. 3 to 6. In addition, D type flip 70 knobs 9 and 1
1 latches the signal supplied to the D input terminal at the rising edge of the clock input. Figure 3 (A> to Figure 3 (G)) show the appearance timing of the rising edge and falling edge of input signal a and the \''1111 reappearance timing of π-phase H output f as a clock. The phase of IL 7r phase output is controlled so that
FIG. 2 is a waveform diagram of multiple Y] when C's is set;
Figure 3 (Δ) is the waveform of the O-phase output g, Figure (13) is the waveform of the π-phase output, Figure 3 (C) is the waveform of the input signal a, Figure 3 (13) is the waveform of the π-phase output.
]) is the waveform of the Q output l) of the 1] type flip 70 knob 9, and (E) is the Q output C of the [) type flip 70 knob 11.
The waveform in the same figure () is the output e of the exclusive OR gate 10.
(G) is the waveform of the output d of the exclusive OR gate 12.
The waveforms of each are shown. Figure 4 (A) to Figure 4 (
G) is the third signal when the phase of the input signal a advances and the appearance timing of the rising edge and the rising edge in the input signal @a is shifted ahead of the appearance timing of the rising edge of the π-phase output f. The waveforms of the same signals as in each of Figures (A) to (G) are shown. Also, the fifth
In the diagrams (A> to (G)), the phase of the input signal a is delayed, and the appearance timing of the complete rising edge and falling edge in the input signal a is later than the appearance timing of the π-phase output f]- The waveforms of the same signals as shown in FIGS. 3(A) to 3(G) in the case of deviation are shown respectively.As is clear from FIGS. 3 to 5, the output e of the exclusive OR gate 10 occurs every time the rising and falling edges of the input signal a arrive, and determines the phase relationship between the input signal a and the π-phase output (that is, the rising edge and falling edge of the input signal a and the π-phase output) The output d of the exclusive OR gate 12 is a pulse whose pulse width is equal to the pulse width of the O-phase output g and the π-phase output [. Then, when the timing of appearance of a rising edge and a falling edge in input signal a coincides with the timing of appearance of a rising edge of π-phase output f, the pulse width of output e of exclusive OR gate 10 becomes exclusive OR. Game 1-1
It becomes equal to the pulse width of the output d of 2. Also, the input signal a
When the phase of input signal a advances, the pulse width of output e becomes wider than the pulse width of output d, and conversely, when the phase of input signal a lags, the pulse width of output e becomes narrower than the pulse width of output (1).
Ru. As described in 1- above, the state of the DC component of the signal obtained by integrating the output of the IJ+adversarial OR gate 10 containing phase information changes depending on the probability of appearance of an edge in the reproduced signal. On the other hand, the signal obtained by integrating the output of the exclusive OR 12 is a signal whose level changes only depending on the probability of appearance of the -ji of the reproduced signal. Therefore, by supplying the outputs e and d of these exclusive OR gates 10 and 12 to the LPF 14 having a differential amplifier configuration, a signal whose level changes only depending on the phase information can be obtained. That is, the D-type flip-flop 9.11 and the exclusive OR gate 10.12 detect the phase difference between the input signal a and the π-phase output f, and as shown in FIG.
A phase comparison means is formed whose output changes linearly with respect to changes in the range from π to π. The D-type flip-flop 9.11 and exclusive OR gate 10.12 forming this phase comparison means are L P F14, VC
Together with O15 and frequency divider 16, pH- is formed, and the appearance timing of the rising edge of the π-phase output [ and the rising edge of the reproduced signal a]
[The appearance timings of the leading edge and the falling edge coincide, and the π-phase output t is reproduced for demodulation [and is output as one piece]. In the above operation, the D-type flip-flop 70 latch 9 latches the input signal @a with the π-phase output f as a recovered clock, and together with the D-type flip-flop 11 and the gate 10.12, outputs the 10-π-phase output t as the recovered clock. Since there is no phase lag, the D-type flip-flop 9 can connect the output of the storage circuit 2 and the output of the storage circuit 2 without using a circuit such as the phase adjustment circuit 8 shown in FIG. I'm glad you can get an equivalent signal. In addition, the differential circuit 1, the double-wave rectifier circuit 3, and the monostable multi-channel 4, in which the human input signal a is directly supplied to the D-shaped knob 9 forming the phase comparison means (-, 1 in Fig. 1), are not required. This simplifies the configuration and eliminates the need for external terminals such as time limit setting terminals, making it easy to integrate into an IC. In addition, in the +2 embodiment, C is the output 1) of the D-type Noripflotso 1) is f - 4, and the π phase output f is the peak 11.
-[The output C of the D-type Norizov 11 becomes the data output and the 0 phase output 0 is reproduced. . Further, in the above embodiment, the oscillation frequency of VCOl5 is twice the clock frequency, but
If the duty cycle of 5 is 50%, VCOl5
The frequency divider 16 can be omitted by making the oscillation frequency equal to the clock frequency. Further, in the above embodiment, the outputs e and d of the exclusive OR gates 10 and 12 are supplied to the 1PF14, which has a configuration in which a differential amplifier and a 6LPF are integrated, and from this l-PF14, the VC
It is assumed that the voltage suppression H of VCOl5 can be obtained, but the voltage control of VCOl5 is
It is obvious that the control I current 1F may be obtained. As detailed above, the clock recovery circuit according to the present invention has two
Since the input signal and the regenerated clock are directly phase-compared using two storage means and one stage of two exclusive ORs to control the phase of the regenerated clock, the configuration is simple and can be used to set a time limit. This eliminates the need for external terminals for external capacitors, etc., and facilitates integration into ICs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional adhesive regeneration circuit, and FIG. 2 is a circuit block diagram showing an embodiment of the present invention.
3 to 5 are output waveform diagrams in each state of the circuit of FIG. 2, and FIG. 6 is a graph showing the characteristics of the phase comparator formed in the circuit of FIG. 2. Explanation of symbols of main parts 9.11...D-type flip-flop 10.12
・・・・・・IJI Alternative OR Gate 1/I・・・・・・
・LPF 15...VC016...
... Frequency divider ill It person Pioneer Corporation agent
Patent Attorney Motohiko Fujimura 13- ・ψ Be Procedure Ne... Authoritative (spontaneous) 1. Display of example Showa 574 [Patent Application No. 129139 2, Name of the invention [1 Tsuku regeneration circuit 3, Person making the amendment i'1 Which relationship Patent applicant Location: 1-4-1 Meguro, Meguro-ku, Tokyo Name name
(501) Pioneer Corporation 4, Agent
104 11 Location 3-10-9-6, Ginza, Chuo-ku, Tokyo
Target of correction Figure Menka 5 Figure

Claims (1)

[Claims] pulse generation means; first storage means for temporarily storing input signals in synchronization with the pulses output from the pulse generation means; and second storage means for temporarily storing the memory contents of the first storage means in synchronization with the pulses. a storage means, a first exclusive OR means for taking an exclusive OR of the input signal and a signal corresponding to the storage contents of the first storage means, and storage contents of each of the first and second storage means. a second exclusive OR means for taking an exclusive OR of two signals (not shown), and repeating the pulse so that the pulse widths of the respective outputs of the first and second exclusive OR means are equal to each other; A clock regeneration circuit characterized in that the pulse is outputted as a regenerated clock while eliminating the phase difference between the pulses of the input signal by controlling the frequency.