JPS6437799A - Dynamic shift register circuit - Google Patents

Abstract

PURPOSE:To facilitate a test by providing a gate circuit to forcibly causing a common clock pulse to be supplied to the clock inverter of a master and a common clock pulse to be supplied to the clocked inverter of a slave to be a level so that all the clocked inverters can be active. CONSTITUTION:Gate circuits 37 and 38 are provided to forcibly cause a master clock phi1, which is supplied to clocked inverters 31-1-31-(n) of the master, and a slave clock phi2, which is supplied to clocked inverters 32-1-32-(n) of the slave, to be the level so that all the clocked inverters 31-1-31-(n) and 32-1-32-(n) can goes to be active. Thus, in the test time, etc., the level is fixed to an H or an L level by a signal from an external part. Then, since all the clocked inverters are made an active condition, all output signals are fixed to the level (H or L) to correspond to an input signal and thus, the test, etc., of the output signal can be easily and exactly executed.