JPS6429956A - Serial interface circuit - Google Patents

Serial interface circuit

Info

Publication number
JPS6429956A
JPS6429956A JP62185903A JP18590387A JPS6429956A JP S6429956 A JPS6429956 A JP S6429956A JP 62185903 A JP62185903 A JP 62185903A JP 18590387 A JP18590387 A JP 18590387A JP S6429956 A JPS6429956 A JP S6429956A
Authority
JP
Japan
Prior art keywords
flop
signal
flip
clock
internal bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62185903A
Other languages
Japanese (ja)
Other versions
JPH053022B2 (en
Inventor
Masayuki Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62185903A priority Critical patent/JPS6429956A/en
Publication of JPS6429956A publication Critical patent/JPS6429956A/en
Publication of JPH053022B2 publication Critical patent/JPH053022B2/ja
Granted legal-status Critical Current

Links

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  • Microcomputers (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To receive an acknowledge signals at a reception side, by outputting the request clock signal of the acknowledge signal from a CPU via an internal bus after completing the data transmission of a shift register by providing a flip-flop. CONSTITUTION:A clock output flip-flop 22 is provided which sets an internal clock CK and a signal (h) from the CPU via the internal bus 20 as input I1 and I2, respectively, and outputs the input CK and (h) selectively by a control signal phi2 inputted from the CPU separately and a control signal phi3 that is the Q-output of the flip-flop 19. And after the data transmission of the shift register is completed, a control pulse is outputted via the internal bus and the clock output flip-flop. In such a way, it is possible to receive the acknowledge signal at the reception side.
JP62185903A 1987-07-24 1987-07-24 Serial interface circuit Granted JPS6429956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62185903A JPS6429956A (en) 1987-07-24 1987-07-24 Serial interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62185903A JPS6429956A (en) 1987-07-24 1987-07-24 Serial interface circuit

Publications (2)

Publication Number Publication Date
JPS6429956A true JPS6429956A (en) 1989-01-31
JPH053022B2 JPH053022B2 (en) 1993-01-13

Family

ID=16178897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62185903A Granted JPS6429956A (en) 1987-07-24 1987-07-24 Serial interface circuit

Country Status (1)

Country Link
JP (1) JPS6429956A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068199A (en) * 1991-05-06 1991-11-26 Micron Technology, Inc. Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5068199A (en) * 1991-05-06 1991-11-26 Micron Technology, Inc. Method for anodizing a polysilicon layer lower capacitor plate of a DRAM to increase capacitance
US5084405A (en) * 1991-06-07 1992-01-28 Micron Technology, Inc. Process to fabricate a double ring stacked cell structure

Also Published As

Publication number Publication date
JPH053022B2 (en) 1993-01-13

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