JPS57116431A - Programmable logic array - Google Patents

Programmable logic array

Info

Publication number
JPS57116431A
JPS57116431A JP56001956A JP195681A JPS57116431A JP S57116431 A JPS57116431 A JP S57116431A JP 56001956 A JP56001956 A JP 56001956A JP 195681 A JP195681 A JP 195681A JP S57116431 A JPS57116431 A JP S57116431A
Authority
JP
Japan
Prior art keywords
output
latching function
input
input data
programmable logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56001956A
Other languages
Japanese (ja)
Inventor
Hiroaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56001956A priority Critical patent/JPS57116431A/en
Publication of JPS57116431A publication Critical patent/JPS57116431A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To shorten a cycle time without any external circuit, by providing an internal circuit with a latching function. CONSTITUTION:An input buffer 1A consists of D type FFs 13-0-13-m and has a latching function. The normal signal Ii' and complementary signal (Ii)' of an input Ii (i=0-m) are obtained as the output of the FF13-i. Similarly, an output buffer 5A consists of the stage of an inverter 1 and a group of D type FFs 13-i (j=0-k), and the out-of-phase output Q' of the FF13'-j is used as an output terminal to obtain the latching function. Input data is fetched by a clock pulse 11 and a clock pulse 12 is inputted after the propagation delay time of a programmable logic array PLA to output data which is determined by the input data. The pulse 11 is inputted right after the output data is outputted and latched, and next input data is fetched, thus performing operation in similar sequence. Therefore, a cycle time is shortened up to the propagation delay time.
JP56001956A 1981-01-10 1981-01-10 Programmable logic array Pending JPS57116431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56001956A JPS57116431A (en) 1981-01-10 1981-01-10 Programmable logic array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56001956A JPS57116431A (en) 1981-01-10 1981-01-10 Programmable logic array

Publications (1)

Publication Number Publication Date
JPS57116431A true JPS57116431A (en) 1982-07-20

Family

ID=11516042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56001956A Pending JPS57116431A (en) 1981-01-10 1981-01-10 Programmable logic array

Country Status (1)

Country Link
JP (1) JPS57116431A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62277813A (en) * 1986-03-06 1987-12-02 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Programmable logic device
JPH02171025A (en) * 1988-12-23 1990-07-02 Nec Corp Semiconductor integrated circuit
JPH02133028U (en) * 1989-04-06 1990-11-05

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62277813A (en) * 1986-03-06 1987-12-02 アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド Programmable logic device
JPH02171025A (en) * 1988-12-23 1990-07-02 Nec Corp Semiconductor integrated circuit
JPH02133028U (en) * 1989-04-06 1990-11-05

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