JPS644116A - Frequency dividing circuit - Google Patents

Frequency dividing circuit

Info

Publication number
JPS644116A
JPS644116A JP15791387A JP15791387A JPS644116A JP S644116 A JPS644116 A JP S644116A JP 15791387 A JP15791387 A JP 15791387A JP 15791387 A JP15791387 A JP 15791387A JP S644116 A JPS644116 A JP S644116A
Authority
JP
Japan
Prior art keywords
circuit
output
turned
transfer gate
high level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15791387A
Other languages
Japanese (ja)
Inventor
Shoichi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP15791387A priority Critical patent/JPS644116A/en
Publication of JPS644116A publication Critical patent/JPS644116A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a frequency dividing circuit operated by a single power supply by feeding back the output of a differential type inverter circuit to an input terminal of the inverter circuit via a 1st transfer gate buffer circuit and a 2nd transfer gate buffer circuit. CONSTITUTION:With the output of a buffer circuit 12 at a low level, when an input clock CK reaches a high level and the 2nd transfer gate TG2 is turned on, the output of the differential inverter circuit 11 reaches a high level after its propagation delay time tpd. In such a case, the 1st transfer gate TG1 receiving an inverted clock signal CK is till turned off and the output of the circuit 12 remains at a low level. When the gate TG1 is turned on, the output of the circuit 12 goes to a high level and, hen the gate TG2 is turned on in such a state, the output of the circuit 11 goes to a low level after the time tpd. The similar operation is repeated every time the gates TG1, TG2 are turned on/off and 1/2 frequency division is implemented.
JP15791387A 1987-06-26 1987-06-26 Frequency dividing circuit Pending JPS644116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15791387A JPS644116A (en) 1987-06-26 1987-06-26 Frequency dividing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15791387A JPS644116A (en) 1987-06-26 1987-06-26 Frequency dividing circuit

Publications (1)

Publication Number Publication Date
JPS644116A true JPS644116A (en) 1989-01-09

Family

ID=15660191

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15791387A Pending JPS644116A (en) 1987-06-26 1987-06-26 Frequency dividing circuit

Country Status (1)

Country Link
JP (1) JPS644116A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6411416A (en) * 1987-07-03 1989-01-17 Nippon Telegraph & Telephone Frequency divider circuit
DE102017126690A1 (en) 2016-11-16 2018-05-17 Ckd Corporation air filter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6411416A (en) * 1987-07-03 1989-01-17 Nippon Telegraph & Telephone Frequency divider circuit
DE102017126690A1 (en) 2016-11-16 2018-05-17 Ckd Corporation air filter

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