JPH02171025A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To keep a level of an output logic data for a prescribed period without interrupting an external control section by keeping outputting of a stored logic data to a logic arithmetic section for a period determined by a prescribed timing depending on a count data. CONSTITUTION:Logic data LD1-LDN are stored in a logic data storage section 1 of a control section 33 and start of count is instructed to a down-counter 32. A readout signal RD being in an active level for a period from the count start of the counter 32 till the input of a count zero signal CZ is outputted to a storage section 1. The logic section 1 keeps outputting of the logic data LD1-LDN for a period when the readout signal RD is in an active level. Thus, the period when output logic data DO1-DON are outputted is coincident with the period when the readout signal RD is in an active level, and the period is set by count data CD1-CDN.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a PLA type semiconductor integrated circuit having a logic operation section composed of an AND section and an OR section.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit has, as shown in FIG. 3, an AND section 21 and an OR section 22 as logic operation sections, and has logic data L D 3 to L input from input terminals.
DN is ANDed together with the signals inverted by the inverters 11 to IN in the AND section 21 by setting circuit connections to the output lines by a plurality of switches 20, and this result is input to the OR section 22. Similarly, circuit connections are set to the output lines by a plurality of switches 20, a logical sum operation is performed, and the logical operation results DO1 to D Ow are output from the output terminals.
It was configured to be output as .

[Problem to be solved by the invention]

The conventional semiconductor integrated circuit described above has a configuration in which the input logic data LD and %LD are processed and output in the AND section 21 and the OR section 22, so that the output logic data DOI~ In order to hold the DOM for the required period, an external control unit inputs logic data LD, ~L to the input terminal.
It is necessary to continue inputting Ds, and during this period, other controls by the external control unit are interrupted, resulting in a disadvantage that control efficiency is reduced.

An object of the present invention is to be able to retain output data for a necessary period without interrupting other controls of an external control unit;
It is an object of the present invention to provide a semiconductor integrated circuit that can improve the control efficiency of this control section.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a logic data storage section that stores input logic data from the outside and outputs it at a predetermined timing for a predetermined period, and a logic data storage section that stores logic data input from the outside and outputs it at a predetermined timing for a predetermined period of time. a logical operation section including a logical product section and a logical sum section that perform a product operation and a logical sum operation;
and a storage control section that controls read timing and period of the logical data stored in the logical data storage section.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The logic data storage unit 1 receives the input data D1 . Logical data LD, ~L of ~DIN
D N is written and stored, and the stored logic data L is read out at a predetermined timing and for a predetermined period by a read signal RD.
D, ~LDN is output.

The logical operation unit 2 includes a logical product unit 21 and a logical sum unit 22, and stores logical data LD, ~LD from the logical data storage unit 1.
Performs a logical product operation and a logical sum operation on n, and outputs the results as output logical data D○1 to DOM. The AND section 21 and the OR section 22 have the same circuit configuration as the conventional example.

The storage control section 3 includes a count data storage section 31. It includes a down counter 32 and a control section 33, and input data D1. ~D
Count data CD of IN.

~CDN is stored, and at a predetermined timing, a read signal RD is output for a period according to the count data CD and ~CDN to control the read timing and period of the logical data storage section 1.

FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

When the write signal WT is at an active level, the input and output data DIl-DIN are count data CD1-CD that determine the output period of the output logic data DO1-DOM, and the logic data LD of the logic operation pair that follows, LD, - It is composed of LDN.

The logic data storage unit 1 stores logic data L D , t to L D N in the latter half of the write signal WT.

The count data storage section 31 stores the count data CD, .about.CDN under the control section 33, and sets the values of the counter data CD, .about.CDN in the down counter 32.

The down counter 32 counts the clock signal CK under the control unit 33, and when the count result matches the set value of the count data CD, ~CDN, that is,
Count data CD.

~ Count down from the CDN value and the value is “0”
When it reaches °', a count zero signal CZ is output.

The control unit 33 stores logical data LD,
After ~LDN is stored, it instructs the down counter 32 to start counting, and outputs a read signal RD that is at an active level for a period from the start of counting of the down counter 32 until the count zero signal CZ is input. This read signal R
During the period when D is at the activation level, the logic data storage unit l continues to output the logic data L D s to LDN.

Therefore, the period during which the output logic data D01-DOM are output coincides with the period during which the read signal RD is at the active level, and this period can be set by the count data CD, -CDN.

Note that input data D1. The processing status for ~DIN is output to the outside by a status signal SS.

〔Effect of the invention〕

As explained above, the present invention stores logic data in the logic data storage section, and continues to output the stored logic data to the logic operation section at a predetermined timing for a period determined by count data. As a result, the output logic data can be independently held for a predetermined period without interrupting the external control section, which has the effect of improving the control efficiency of the control section.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram of signals of various parts to explain the operation of the 11 example shown in Fig. 1, and Fig. 3 is a conventional semiconductor integrated circuit. FIG. 2 is a circuit diagram showing an example of a circuit. 1...Logic data storage section, 2...Logic operation section, 3.
...Storage control unit, 20...Switch, 21...Logic product unit, 22...Logic sum unit, 31...Count data storage unit, 32...Down counter, 33...Control unit , ■1~IN...Inverter.

Claims (1)

[Claims] A logic data storage unit that stores input logic data from the outside and outputs it at a predetermined timing for a predetermined period, and performs predetermined AND operations and OR operations on the logic data output from this logic data storage unit, respectively. 1. A semiconductor integrated circuit comprising: a logic operation section including an AND section and an OR section; and a storage control section that controls readout timing and period of logic data stored in the logic data storage section.