JPS6020635A - Programmable logic array - Google Patents

Abstract

PURPOSE:To attain high speed operation without attending generation of malfunction due to slow operating speed of an AND array by separating the operation of the AND array and the operation of an OR array. CONSTITUTION:An input signal is inputted to the AND array 1 from an input register 3 at a time I , and the operation of the AND array 1 is executed between times I and II. A signal of the AND array 1 is inputted to a flip-flop circuit (FF)5 at the time II and stored therein. When the next signal is inputted to the AND array at a time III, the signal stored in the FF5 is inputted to the OR array 2 and the operation of the AND array 1 and the operation of the OR array 2 are executed at the same time between times III and IV. Further, the next output signal of the AND array 1 is inputted to the FF5 at the time IV, an output signal is outputted from an output register 4 at a time V, and the signal is inputted from the input register 3 to the AND array 1 at the same time and the signal is inputted to the OR array 2 from the FF5.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to improvements in programmable logic arrays. In particular, the present invention relates to an improvement in a programmable logic array that prevents malfunction even when the parasitic capacitance is large and the signal propagation time is slow due to the parasitic capacitance.

(2) Background of the technology A programmable logic array performs specific arithmetic processing on binary information input via arbitrary parallel signal lines, and outputs the resulting information via arbitrary parallel signal lines. It refers to a binary information calculation element, and has the feature that the content of the specific calculation processing can be selected as desired. Generally, this is realized using an MIS type semiconductor element.

(3) Prior Art and Problems An example of a programmable logic array in the prior art is shown in FIG. In the figure, 1 surrounded by a broken line is A
It is an ND array, and consists of k X-rays 11, X-rays 12, and m Y-rays 13 arranged orthogonally thereto. For each X-ray 11 and X-ray 12, 1
The input signal and its inverted signal are input. Each Y line 13 is connected to a power supply via a load resistor 14. X
Line 11. A switching element 15 is provided at the intersection of each of the X-rays 12 and each of the X-rays 13;
Whether or not the drains of these switching elements 15 are electrically connected to the X-rays 13 is programmable.

2 surrounded by a broken line is an OR array, and there are m X-rays 23 connected to each of the X-rays 13 of the AND array, and n X-rays 21 are provided perpendicularly to these. Each X-ray 21 is connected to a power source via a load resistor 24. Switching elements 25 are provided at the intersections of each of the X-rays 23 and each of the X-rays 21, and the drains of these switching elements 25 are connected to the X-rays 21.
Whether or not it is electrically connected to is programmable.

In summary, the input signals input to arbitrary X-rays 11 and X-rays 12 of AND array 1 are output to X-rays 13 according to the program,
There may also be cases where it is not output.

Since each of the X-rays 13 of AND array 1 is connected to the corresponding X-ray 23 of OR array 2, the signal processed according to the program of AND array 1 is directly output to the corresponding X-ray 23 of OR array 2. However, this signal is also output to a predetermined X-ray 21 according to the program.

By the way, the programmable array as described above is
As shown in the figure, an input register 3 and an output register 4 are generally provided at the input end and the output end, respectively.

The input register 3 has a plurality of (in this example, two) parallel input signal lines 31, and receives a clock signal (of the clock CK).
It has a function of inputting an input signal from the parallel input signal line 31 and outputting it to the AND array l based on the first clock signal).

The output register 4 has a plurality of (n in this example) parallel output signal lines 41, and receives the clock signal (of the clock CK).
It has a function of outputting an output signal to the parallel signal line 41 based on the clock signal (other clock signal).

In the programmable logic array according to the prior art described above, the clock signal is given to the input register and the output register, so the operation of the programmable logic array is completed in one clock period. It is essential that the Otherwise, some signal will drop out of the output signal, so to speak.
This is because it will cause a malfunction.

However, as the number of X-rays, X-rays, and Y-rays in a programmable logic array increases and their lengths increase, parasitic capacitance increases, and the computation time and signal propagation time inevitably tend to increase. This drawback can be easily overcome by increasing the length of the clock signal, but this method is not desirable because it delays the information processing speed.

Therefore, it has been desired to develop a programmable logic array that effectively prevents malfunctions without slowing down the information processing speed even when the computational capacity of the programmable logic array becomes large and the parasitic capacitance is large.

(4) Purpose of the Invention The purpose of the present invention is to meet this demand, and to provide a programmable logic array that has high calculation speed without causing malfunctions even when the calculation capacity is large and the parasitic capacitance is unavoidably large. It's about doing.

(5) Configuration of the Invention The configuration of the present invention includes: an AND array that receives a signal based on a first clock signal and executes an operation; an OR array that receives an output signal of the AND array and executes an operation; In a programmable logic array that outputs an output signal of an OR array based on another clock signal,
connected to each of the output signal lines of the AND array,
A second clock signal reads each of the output signals of the AND array, and a third clock signal inputs the next signal to the AND array. In other words, the present invention provides a programmable logic array characterized by having a signal storage means for outputting to an input signal line. A signal storage means 5 such as a flip-flop circuit which operates based on a clock signal governing the operation of the input register 3 and output register 4 attached to the programmable logic array described above is inserted, and (b) the first clock The input signal is input from the input register 3 to the AND array l, where the operation is executed, and (c) the second
The output signal of the AND array 1 is inputted to the flip-flop circuit 5'8 with the clock signal (inverted signal of the first clock signal), and (d) the third clock signal (inverted signal of the first clock signal) The signals stored in the above-mentioned flip-flop circuit 5 etc. are sent out to the respective corresponding input signal lines of the above-mentioned OR array 2, and the next input signal is sent from the input register 3 to the AN
Input it to the D array 1, execute the calculation, and input the next output signal of the above AND array 1 to the flip-flop circuit 5 using the fourth clock signal (inverted signal of the second clock signal). (to) An output signal is output from the output register 4 using the fifth signal (a signal of the same type as the first and third clock signals), and an AN signal is output from the input register 3.
An input signal is input to the D array 1, and a signal stored in the Noritsu flop circuit 5 is input to the OR array 2.

As a result, the operation in AND array 1 and the operation in OR array 2
This completely separates the operation in the AND array 2 to prevent malfunctions caused by the slow operation speed in the AND array 1, and simultaneously performs the operation in the OR array 2 and the next operation in the AND array 1. This also prevents time loss. That is, as shown in the timing chart shown in FIG. 3, an input signal is input from the input register 3 to the AND array 1 at time I, an operation of the AND array l is executed between l-11, and an AND array is input at time II. The signal of array 1 is input to the flip-flop circuit etc. 5 and stored there, and at time tlI, the next signal is input to the AND array, and the signal stored in the flip-flop circuit etc. 5 is input to the OR array 2. III-
During IV, the operation of AND array l and the operation of OR array 2 are executed simultaneously, and at time IV, the next output signal of AND array I is input to flip-flop circuit 5, and at time ■, the output signal is input to output register 4. At the same time, signals are input from the input register 3 to the AND array 1, and signals from the flip-flop circuit 5 and the like are input to the OR array 2, so that no time loss occurs at all.

(6) Embodiments of the Invention Below, a programmable logic array according to an embodiment of the present invention will be further described with reference to the drawings.

Referring to FIG. 4, one unit of the signal storage means 5 according to the subject matter of the present invention is shown. In this example, it is a kind of flip-flop circuit, and one transmission switching element 5 is used.
1 and two inverters 52 and 53. This flip-flop circuit takes in a signal at the timing when the inverted clock signal CK becomes H logic (time II in the above timing chart), and outputs the next clock signal G.
A signal is output at the timing when K becomes H logic (time III in the above timing chart), and this state is maintained until the timing when clock signal CK becomes H logic (time V in the above timing chart).

Referring to FIG. 5, a programmable logic array according to the gist of the present invention is shown in which the signal storage means 5 described above is inserted between the AND array 1 and the OR array 2.

At the timing when the clock signal CK is at H logic (time I in the above timing chart), the first signal from the input register 3 is input to the AND array I, and an operation is executed. At the timing when the clock signal CK becomes L logic (time II in the above timing chart), the first signal is taken into the flip-flop circuit 5 and stored. Next clock signal CK
At the timing when becomes H logic (time III in the above timing chart), the first signal is input to the OR array 2 and is calculated there, and the second signal is input to the AND array l.
The signal is input to the output register 4, is calculated here, and is output to the output register 4. The second signal is stored from the AND array 1 into the flip-flop circuit 5 at the next timing when the clock signal CK becomes L logic (time IV in the above timing chart). At the H logic of the next clock signal CK (time ■V in the timing chart above), the first signal is output to the output register 4.
At the same time, the second signal is input from the flip-flop circuit 5 to the OR array 2, and an operation is executed.

As explained above, two signals are transmitted from the input side to the output side in the same two clock times, and during that time they are cut off by the flip-flop circuit 5.
The penalty due to delay speed in D array l is completely eliminated. Moreover, since two consecutive signals are processed at the same time in two clock periods, no time loss occurs at all.

Since the programmable logic array described above can be easily manufactured using a normal manufacturing method for semiconductor devices, a description of the manufacturing process will be omitted.

(7) As described in detail, according to the present invention, it is possible to provide a programmable logic array that has high operation speed without causing malfunctions even when the operation capacity is large and the parasitic capacitance is unavoidably large. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a programmable logic array according to the prior art, and FIG. 2 is a block diagram when the example of the programmable logic array according to the prior art shown in FIG. 1 is used. FIG. 3 is a timing chart illustrating the present invention in detail. FIG. 4 is a wiring diagram showing an example of a signal storage means according to the gist of the present invention, and FIG. 5 is a block diagram of an example of a programmable logic array according to an embodiment of the present invention. 1---AND71/a, 1l---X-ray, 12
-...X-ray, 13...Y-line, 14-load resistance, 15...switching element, 2φ...OR array,
21・--X-ray, 23・War・Y-ray. 24・Life・Load resistance, 25...Switching element, 3
...Input register, 31...Parallel input signal line, 4
...output register, 41...parallel output signal line,
I, Il, III, IV, V---Timing time, 5. Fist/signal storage means (flip-flop circuit), 51Φ/φ transmission switch element,
52.53---4 number-175- L J

Claims (1)

[Claims] An AND array that receives a signal as input based on a first clock signal and performs an operation, an OR array that receives an output signal of the AND array and performs an operation, and an output of the OR array based on another clock signal. A programmable logic circuit that outputs signals is connected to each of the output signal lines of the AND array, reads each of the output signals of the AND array based on a second clock signal, and transmits the next signal to the AND array. A programmable logic array comprising signal storage means for outputting each of the signals to corresponding detent signal lines of the OR array based on an input third clock signal.