JPH04172715A - Coincidence detection circuit - Google Patents

Abstract

PURPOSE:To realize a coincidence detection circuit capable of high speed operation by employing simple 2-input OR and AND gates for a logic gate section and inverting either of a comparison data or a compared data. CONSTITUTION:A counter 10 is a 4-bit up-counter outputting compared data Q1-Q4 while increasing monotonously in response to an input clock phi. Moreover, a logic gate section 11 has plural input terminals provided corresponding to each 1-bit of the compared data Q1-Q4 and plural other input terminals provided corresponding to each bit of the comparison data in plural bits. The logic gate section 11 compares the comparison data with the compared data Q1-Q4 and outputs a coincidence detection signal P when they are coincident. Thus, the coincidence detection function is realized with simple circuit constitution and high speed operation is attained.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a coincidence detection circuit configured with a semiconductor circuit device, and in particular, the present invention relates to a coincidence detection circuit configured with a semiconductor circuit device, and in particular, the present invention relates to a coincidence detection circuit configured with a semiconductor circuit device. It is used for timers etc.

(Prior Art) In general, a single pit coincidence detection circuit is basically configured by exclusive OR. Furthermore, for example, in a multi-bit (four-bit) coincidence detection circuit as shown in FIG.
As shown in ttiA (a) in the same figure, coincidence detection is performed by further calculating the logical sum for each exclusive logical sum. Here, 1 is a periodic clock input line, 2 is a 4-bit up counter, 3 is a comparison data input line, 4 is a compared data input line, 5 is an exclusive OR, 6 is a logical OR, and 7 is a match detection output line , 8 are RS flip-flops.

In other words, in such a multi-bit coincidence detection circuit, the comparison data and the compared data are determined, for each single bit, by exclusive OR 5 of each bit, whether they are both "1" or not, or whether they are both "0". Then, when all the bits match, that is, both are "1" or both are "0", a match detection output P is output.

Specifically, for example, it is assumed that the preset 4-bit comparison data is "1°", "0", "0", and "1°". This comparison data passes through the comparison data input line 3, respectively.
It is input to one input terminal of exclusive OR 5. Also,
As shown in the time chart of FIG. 7, from the 4-bit up counter 2, the compared data Q, ~Q
4 are respectively input to the other input terminal of the predetermined exclusive OR 5. Then, when all the bits match, that is, when the compared data Q1 to Q4 become "1", "0", "0", and "1", "02" is output from all exclusive ORs 5. Therefore, "02" is output from all exclusive ORs 5. , the logical sum 6 outputs "1" as the match detection output P.

However, in the multi-bit coincidence detection circuit described above, one exclusive OR 5 is required for one bit of comparison data. In other words, the same number (for example, four) of exclusive ORs 5 are required depending on the number of data bits (for example, four bits) of the comparison data.

Therefore, in order to obtain a coincidence detection output, the number of switching elements constituting one exclusive OR 5 is required to be equal to the number of data bits.

Therefore, the coincidence detection circuit alone becomes a large-scale circuit group, which is disadvantageous for LSI implementation.

In the field of LSI, the circuit configuration of the exclusive OR 5 is shown in FIG.
It is known that the number of constituent elements has been reduced by developing the exclusive OR 5 into a circuit configuration as shown in Figure 9, for example. The circuit configuration of OR5 has the disadvantage that it is not suitable for high-speed operation.

(Problem to be solved by the invention) As described above, in the conventional coincidence detection circuit, one exclusive OR was required for one bit of comparison data, so the number of switching elements constituting the coincidence detection circuit increased. death,
LSI implementation had disadvantages. Also, an exclusive OR of circuit configurations suitable for LSI implementation was considered, but
The drawback was that it was not suitable for high-speed operation.

The present invention has been made to solve the above drawbacks,
It is an object of the present invention to provide a coincidence detection circuit that can realize a coincidence detection function with a simple circuit configuration and can operate at high speed.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the coincidence detection circuit of the present invention has the following features:
The apparatus includes first means for outputting a plurality of bits of first data while changing the data in response to an input clock. Also,
a plurality of one input terminals provided corresponding to each one bit of the first data; and a plurality of one input terminals corresponding to each one of the plurality of input terminals, and corresponding to each one bit of the plurality of second data. and a plurality of other input terminals provided respectively, and includes second means for outputting a coincidence detection signal when the first data and the second data match. Furthermore, third means is connected to the output terminal of the second means and stores the coincidence detection signal; and fourth means for inverting either one of the first and second data.

The coincidence detection circuit of the present invention uses an up counter as the first means. Further, a down counter is used as the first means.

The coincidence detection circuit of the present invention includes means for using the output signal from the third means as a set or reset signal for setting the initial state of the first means.

In the coincidence detection circuit of the present invention, the second means includes the first
or there are a number corresponding to the number of bits of the second data,
a group of two-input NAND circuits each having one input terminal input with a predetermined one bit of the first data and the other input terminal receiving a predetermined one bit of the second data; It is composed of a plurality of input NAND circuits into which output signals from each of the NAND circuit groups are input.

In the coincidence detection circuit of the present invention, the second means includes the first
or there are a number corresponding to the number of bits of the second data,
a group of two-input NOR circuits each having one input terminal receiving a predetermined one bit of the first data and the other input terminal receiving a predetermined one bit of the second data; and a plurality of input NOR circuits into which output signals from each of the NOR circuit groups are input.

(Operation) According to such a configuration, for example, a simple logical sum or logical product of two-person gates can be used as the second means. Also,
One of the first and second data is inverted. At this time, a plurality of match detection outputs are output, but it is possible to perform match detection by detecting only the first match among the plurality of match detection outputs. Therefore, the coincidence detection function can be realized with a simple circuit configuration, and high-speed operation is possible.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a coincidence detection circuit according to an embodiment of the present invention.

10, the compared data (first
This is a 4-bit up counter that outputs data Q1 to Q4 while monotonically increasing.

Reference numeral 11 denotes one of a plurality of input terminals provided corresponding to each one bit of the compared data Q1 to Q4, and a plurality of bits of comparison data (second This is a logic gate section having a plurality of other input terminals provided corresponding to each one bit of data (2). In the logic gate section 11, the comparison data and the compared data Q1 to Q4 are compared, and when they match, the match detection circuit P outputs an output. The number of logic gate sections 11 corresponds to the number of bits of the compared data Q1 to Q4 or comparison data, and each logic gate section 11 has one input terminal connected to the compared data Q1 to Q4 or the number of bits of the compared data.
, ~Q4, and a two-input NO in which a predetermined bit of comparison data is input to the other input terminal, respectively.
It is composed of an R circuit group 12 and a plurality of input NOR circuits 13 into which each output signal from the NOR circuit group 12 is input. The NOR circuit group 12 corresponds to the exclusive OR circuit 5 in FIG. 6 replaced with a NOR circuit.

Preset four-bit comparison data is inverted by an inverter 14 and then input to the other input terminal of each of the NOR circuit group 12. Further, each output of the NOR circuit group 12 is further input to a NOR circuit 13.

The output of the NOR circuit 13 becomes a coincidence detection output P, and this coincidence detection output P is input to the reset terminal R of the RS flip-flop 15 and stored. On the other hand, the compared data Q, ~Q4 output from the 4-bit up counter 10
is input to the NOR circuit 16. In addition, NOR circuit 1
The output of 6 is the set terminal S of RS flip-flop]5.
is input to.

Next, the operation of the coincidence detection circuit will be explained with reference to the time chart shown in FIG.

Now, assume that in the coincidence detection circuit shown in FIG. 1, the preset four-bit comparison data is "1", "0", "0", and "1". From the four-bit up counter 10,
Monotonically increasing compared data Q, ~Q4 are output, and these compared data Q1 ~ Q4 are respectively output from the NOR circuit group 12.
is input to one of the input terminals. The comparison data is inverted by the inverter 14 and then inputted to the other input terminal of the NOR circuit group 12 as inverted data "0", "1", and "O'". Here, when the comparison data and the compared data match, all outputs of the NOR circuit 12 become "0", so the match detection output P output from the NOR circuit 3 becomes "1". Inverted data “0゛” “1” “0”, compared data Q, ~Q where all NOR outputs become logic “0”
4 is “0”0”0゛0” to “1”1” “]”1”
During -cycles up to “11 “0” “01 “1”
As the first, then the fifth thing will happen. This can be dealt with as follows. In other words, it is noted that the match between the comparison data and the compared data is always the first of the four times when the match detection output P becomes "1". In other words, the first match detection output P is data indicating an accurate match, and the subsequent five matches are false data.

Therefore, if the match between the comparison data and the compared data is always detected at the first time, the problem will disappear.

According to such a configuration, it is possible to replace the exclusive ORs, which are required in number corresponding to the number of bits of each data, with a simple logical sum or logical product of two-person gates. Therefore, not only can the circuit configuration be simplified, but also the area occupied on the integrated circuit can be reduced by reducing the number of switching elements. Furthermore, since the number of switching elements is small, there are fewer voltage change points up to the output, and it is also possible to operate at relatively high speed.

In addition, in the above embodiment, compared data Q1 to Q4
Although an up counter that monotonically increases is used, a down counter that monotonically decreases compared data Q, to Q4 may also be used. Further, although the comparison data is inverted by the inverter 14, a configuration may be adopted in which the compared data is inverted instead of the comparison data.

FIG. 3 shows a coincidence detection circuit according to another embodiment of the present invention.

In this embodiment, the 4-bit up counter 10A is provided with a function of inverting the compared data Q1 to Q4, so that the inverted data Q1 to Q4 of the compared data Q1 to Q4 are used. Further, a NAND circuit group 12A is used as a logic gate group to which the inverted data Q1 to Q4 of the data to be compared is inputted to one input terminal. The logic gate to which the output of the NAND circuit group 12A is input includes a NAND circuit 13A.
is used. The output of the NAND circuit 1.3 A is
The coincidence detection output P is inputted to the reset terminal R of the RS flip-flop 15 and stored. In addition, the input terminal is a 4-bit up counter IOA
A NAND circuit 1 is connected to the logic gate whose output terminal is connected to the set terminal S of the RS flip-flop 15.
6A is used.

Even with such a configuration, the operation is the same as that of the coincidence detection circuit shown in FIG. Effects can be obtained. In other words, the match detection output P becomes "1" four times, but the first time is always an accurate match, so the first time is used to detect the match between the comparison data and the compared data. be able to.

FIG. 4 shows a coincidence detection circuit according to another embodiment of the present invention. Here, FIG. 5 shows a time chart showing the basic operation of the coincidence detection circuit shown in FIG. 4.

In this embodiment, the inverted data Q, ~Q4 of the compared data
An N+1 counter 10B is used as the counter that outputs. Further, the output signal O of the RS flip-flop 15 is used as a set or reset signal for setting the initial state of the N+1 counter IOB. That is, the NOR circuit 17 is connected between the output terminal of the RS flip-flop 15 and the N+1 counter 10B.

According to such a configuration, after the comparison data and the compared data match, the cycle of the compared data can be changed arbitrarily by setting or resetting to the initial state. In other words, the first coincidence detection circuit P can end the cycle and start counting the next cycle.

[Effects of the Invention] As described above, the coincidence detection circuit of the present invention provides the following effects.

The coincidence detection circuit of the present invention focuses on the fact that a coincidence detection circuit used in a timer or the like is configured with a means for generating compared data or a device that monotonically increases or decreases the output of an up counter, a down counter, etc. The configuration of the detection circuit is such that a simple logical sum or logical product of two-person gates is used in the logic gate section, and one of the comparison data and the data to be compared is inverted. Further, in such a configuration, it is possible to detect a match by outputting a plurality of match detection outputs or by detecting only the first match among a plurality of match detection outputs. Therefore, the coincidence detection function can be realized with a simple circuit configuration.
It is also possible to provide a coincidence detection circuit that can operate at high speed◇

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of a coincidence detection circuit according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the coincidence detection circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram showing the basic configuration of a coincidence detection circuit according to another embodiment of the present invention, and FIG. 5 is a circuit diagram showing the basic configuration of a coincidence detection circuit according to another embodiment of the present invention. A time chart showing the operation of the detection circuit, FIG. 6 is a circuit diagram showing a conventional coincidence detection circuit, FIG. 7 is a time chart showing the operation of the coincidence detection circuit of FIG. 6, and FIG.
9 and 9 are circuit diagrams respectively showing the configuration of an exclusive OR used in conventional LSI implementation. 10, IOA...4-bit up counter, 1, O
B...N+l counter, 11...Logic gate section, 1
2...NOR circuit group, 12A...NAND circuit group,
13.16.17...NOR circuit, 13A, 16A・
...NAND circuit, 14...inverter, 15...
RS flip flop. Figure 1 Figure 2 Figure 4 Figure 6 Figure 7 Figure s8 Figure 9

Claims (1)

[Scope of Claims] (1) A first means for outputting a plurality of bits of first data while changing it according to an input clock; a plurality of one input terminals, and a plurality of other input terminals respectively provided corresponding to one input terminal of the plurality and corresponding to each bit of the second data of the plurality of bits. , a second means that outputs a coincidence detection signal when the first data and the second data match; and a second means that is connected to the output terminal of the second means and stores the coincidence detection signal. 3, and a fourth means for inverting either one of the first and second data before the first and second data are input to the second means. A match detection circuit featuring: (2) The coincidence detection circuit according to claim 1, wherein an up counter is used as the first means. (3) The coincidence detection circuit according to claim 1, wherein a down counter is used as the first means. (4) The coincidence detection circuit according to claim 1, further comprising means for using the output signal from the third means as a set or reset signal for setting an initial state of the first means. (5) The number of the second means corresponds to the number of bits of the first or second data, and a predetermined 1 bit of the first data is input to one input terminal of each, and each of the second means has a number corresponding to the number of bits of the first or second data. a two-input NAND circuit group into which a predetermined 1 bit of the second data is input to the other input terminal; and a multi-input NAND circuit into which each output signal from the two-input NAND circuit group is input.
Claim 1 characterized in that it is comprised of a D circuit.
Coincidence detection circuit as described. (6) The number of the second means corresponds to the number of bits of the first or second data, and a predetermined 1 bit of the first data is input to one input terminal of each, and each of the second means has a number corresponding to the number of bits of the first or second data. Consisting of a two-input NOR circuit group into which a predetermined 1 bit of the second data is input to the other input terminal, and a multiple-input NOR circuit into which each output signal from the two-input NOR circuit group is input. 2. The coincidence detection circuit according to claim 1, wherein: