JPS61284676A - Logical value comparison and decision circuit - Google Patents

Abstract

PURPOSE:To set a decision strobe over plural basic periods by holding expected value data and control data for comparative decision making over plural basic periods and outputting the held data according to the time series order of the decision strobe. CONSTITUTION:A basic period clock 120 is converted by a clock control circuit 101 into a clock having a period which is the integer multiple of a basic period and inputted to a data holding circuit 102 from OR gates 107-110; and the control and expected value data 130 and 129 are held for two basic periods and outputted from the circuit 102 to multiplexers 115 or 116 alternately in input order with a time difference. A data selective output circuit 103 sets the decision strobe for two basic periods to output data having a number coincident with the input number of the clock 120 from the multiplexer 115 or 116 and outputs a number specified when the decision strobe signal is supplied to a comparative decision part 104; and data 139 and 140 based upon a delay strobe signal 143 are compared with the output value 141 of a logic circuit to be tested to make a comparison and decision for two basic periods.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic value comparison and determination circuit used in a logic circuit,
In particular, the present invention relates to a logic value comparison/determination circuit for comparing and determining an output from a logic circuit under test and an expected value.

[Background of the invention]

A conventional device of this kind is equipped with a plurality of comparison/judgment circuits, as described in Japanese Patent Application Laid-open No. 57-20674 (in particular, FIG. There are known devices that test logic circuits under test. However, in logic circuit test equipment, 1 judgment strobe is replaced by 2 strobes.
There are cases where it is necessary to set the period over a period longer than the basic period, and in conventional devices, no consideration was given to this point at all.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic value comparison/judgment circuit that can set a decision strobe that provides timing for comparison/judgment over a plurality of basic cycles.

[Summary of the invention]

The present invention maintains the expected value data and control data used for comparison judgment up to the time range in which the judgment strobe is set, and outputs them in time series according to the number of judgment strobes. Comparison and judgment are performed using expected value data and control data corresponding to the order.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described using the block diagram of FIG. 1 and the time chart of FIG. 2. FIG. 1 is a block diagram of this embodiment, which is composed of a clock control circuit lot, a data holding circuit 102, a data selection output circuit 103, and a comparison/judgment section 104. Hereinafter, for convenience of explanation, a case will be described in which the determination strobe is set over two periods.

The clock control circuit 101 receives a basic cycle clock 120 and an initial value setting signal 121 shown in FIG. 2A.

For example, a 1-bit counter 105. It is composed of a decoder 106 and OR gates 107 to 110. The counter 105 is set to an initial value at the start of counting by an initial value setting signal 121, and counts up by a basic cycle clock 120. At this time, parallel output 1 of counter 101
22 outputs two different logic values (logic "1" and logic "0") for each basic cycle as shown in FIG. 124, the basic period clock 120 (
2A) through the gates 108 and 110, or
Alternatively, it controls whether or not it passes through gates 107 and 109.

Therefore, from the output 125 of the clock control circuit 101,
A data holding clock having a period equal to two periods of the basic period clock 120 shown in FIG. Clock is output. Note that the clocks output from outputs 127 and 128 are in phase with the data holding clocks output from outputs 125 and 126, respectively.

The data holding circuit 102 is composed of, for example, four D-type flip-flops (t)-FF) 111 to 114, and includes expected value data 129 and several bits of control data for comparison and judgment with the response from the logic circuit under test. 130 and the data holding clocks 125 to 128 for holding the expected value data 129 are input.

Expected value data and control data are supplied every basic cycle, as shown in FIG. 2B, and are supplied to the data holding circuit 102.
Then, the data holding clocks 125 to 128 cause the second
As shown in FIG. H1i, the expected value data 129 and control data 130 are held for two basic periods.

Data selection output circuit 103 through outputs 131 to 134
supply to

The data selection output circuit 103 includes, for example, a multiplexer 115, 116.
, and a decoder 118. Above counter 1
19, a determination strobe as shown in FIG. 2 J is connected to the terminal 13.
It is input from 5. In the determination strobe (FIG. 2 J), the N-th and N+1-th determination strobes are set within the N-th cycle and the N+1-th cycle, respectively, but the N+2-th and N+3-th determination strobes teeth,
are set within the N+3th period and within the N+4th period, respectively,
The setting range spans two fundamental periods. The counter 119 counts the determination strobes and outputs a logical value corresponding to the count number to its parallel output 137, as shown in FIG. 2K. Note that the decoder 118 is unnecessary only when the counter is 1 bit (therefore, only when the strobe setting range is within 2 basic periods), and the parallel output signal 137 and multiplexer selection signal 138 match, but for convenience of explanation, , a decoder 118 is provided in FIG.

The multiplexers 115 and 116 select the data holding circuit 1 by the multiplexer selection signal 138 (K in FIG. 2).
Expected value data 131, 132 and control data 133, 134 (H, i in FIG. 2) supplied from 02 are selectively outputted through output terminals 139, 140 as shown in FIG. supply to Comparison/judgment section 104
The strobe shown in FIG. 2M, which is a delayed judgment strobe, is supplied by the delay circuit 117, and the expected value data 139 (FIG. 2L) and the output 14 from the logic circuit under test are
A comparison judgment is made with the output value supplied from 1, and the result is outputted through a comparison judgment output 142. Here, the delay time To (FIG. 2) of the delay circuit 117 is determined when the strobe J (FIG. 2) is input to the data selection output circuit 103.
It is sufficient that it is longer than the time T (FIG. 2) until the expected value data L corresponding to the strobe J is output.

In the above configuration, the basic period clock is converted by the clock control circuit 101 into a clock having a period that is an arbitrary integral multiple of the basic period, and is output from each of the OR gates 107 to 110. These clocks are input to D-FFIII-114 of the data holding circuit 102 and are used to hold control data 130 and expected value data 129. Here, 1 expected value data 129 and control data 1
30 is held for two fundamental periods, and then the expected value data 1
D-FFIII to 114 with a time difference in the input order of 29
more sequentially and alternately multiplexer 115 or 116
Output to. The data selection output circuit 103 has N+k
(However, 2, 3, 4...) is set over two basic periods, and the multiplexers 115 and 116 output data with a number that matches the input number of the basic period clock 120, and the judgment strobe signal When given, outputs the data of the specified number. Comparing and determining section 104 receiving these signals compares and determines data 139 and 140 and output value 141 from the logic circuit under test based on delayed strobe signal 143 .

As is clear from the above explanation, according to this embodiment, even when the strobe is set over two basic periods, such as the N+2th determination strobe, the N+2nd period corresponding to the N+2nd strobe can be set. Expected value data and control data can be supplied.

Comparative judgment over two fundamental periods is possible.

In the above explanation, the determination strobe is set within 2 basic periods, but when the strobe is set within m basic periods (m ≥ 2 integer), the number of bits of the counter is K (K is ≧QOg, an integer that satisfies m) may be set to an appropriate value, and D-FFs within the number of data retention times lO2 may be added in accordance with the number of clock signals output from the clock control circuit 101.

〔Effect of the invention〕

As is clear from the above, according to the present invention, it is possible to hold expected value data and control data that are supplied every basic cycle and are used in comparison and judgment over a plurality of basic cycles, and the held data can be output in accordance with the chronological order of the determination strobes, so the determination strobes can be set not only within one basic period but also within any plurality of basic periods.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart of each part of the embodiment of FIG. 101... Clock control circuit, 102... Data holding circuit, 103... Data selection output circuit, 104.
... Comparison and judgment section, 105.119 ... Counter, 10
6,118...Decoder, 107°108.109,
110... OR gate, 111-114... D-type flip-flop, 115, 116... Multiplexer, 117... Delay circuit 6

Claims (1)

[Claims] A logic value comparison/judgment circuit that compares and judges the output value of the logic circuit under test and expected value data, includes a clock control circuit that converts a basic clock with a constant period into a clock that has a period that is an integral multiple of that period, and an output from the circuit. a data holding circuit that holds and outputs input logic data for a time that is an integer multiple of the basic clock based on a clock provided by the basic clock; and a data holding circuit that holds and outputs input logic data for a time that is an integral multiple of the basic clock; The present invention is characterized by comprising a data selection output circuit that selectively outputs data, and a comparison/judgment section that makes a comparison/judgment between the data outputted from the circuit and the output value of the logic circuit under test based on the strobe signal. A logical value comparison judgment circuit.