JPH01138477A - Circuit testing device - Google Patents

Abstract

PURPOSE:To classify differences in response time by small time difference by supplying a strobe pulse through an independent signal line and leading out response output signals at different timing. CONSTITUTION:A level comparator 300 is supplied with a response output signal from a circuit to be tested at an input terminal 301 to decide whether or not an H level and an L level are normal by comparison. Then, a logical comparator group 400 decides whether or not there is the response output signal from the comparator 300 by signal detecting circuits 402 and 403 with strobe pulses STRB1 and STRB2 sent through different transmission lines 415 and 416 and logic comparators 402A and 402B compare the decision result with an expected value signal to decide whether or not it is coincident. Thus, the response time differences are classified by small time differences.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a circuit testing device suitable for testing, for example, a digital circuit incorporated in a semiconductor bulk circuit element.

"Prior Art" Figure 6 shows the overall configuration of a circuit testing device. 100 in the diagram
indicates the circuit under test. This circuit under test 100 is, for example, I
It can be a C memory, a logic circuit, or the like.

A test pattern signal CP is applied to this circuit under test 100 from a pattern generator 200 . pattern generator 20
0 is the expected value pattern signal E in addition to the test pattern signal CP.
' Output terminal 500 for match and mismatch
[2. If necessary, record the judgment output as a failure analysis memo! 7600 so that failure analysis can be performed.

Note that a level comparator 300 is provided between the circuit under test 100 and the logic comparator group 400, and this level comparator 30
0, it is determined whether the level of the response output signal of the circuit under test 100 has a normal H logic level comparator or a normal low logic level VOL, and the normal logic level VO) f
Alternatively, a signal is output assuming that a response output is obtained only when the VOL is provided, and the signal is sent to the logic comparator group 4.
00 for logical comparison.

The level comparator 300 and the logic comparator group 400 are provided with logic comparators equal to the number of output terminals of the circuit under test 100.

In order to be able to test ICs such as LSIs, several hundred sets (9) of level comparators 300 and logic comparators are prepared corresponding to the number of bins of the LSI.

By the way, in order to distinguish between fast and slow response speeds of the circuit under test 100, a plurality of signal detection circuits for detecting the presence or absence of logic judgment output signals are conventionally provided in the logic comparator group 400. Strobe signals with different timings are applied, and the presence or absence of a logic judgment output signal is determined at the time of supply of this strobe signal. Some circuits have a structure in which it is possible to determine whether the response speed of the circuit is fast or slow by checking whether a logic judgment output signal exists or not.

An example is shown in FIG. 300 in the figure is a level comparator;
400 indicates a logical comparator group. The level comparator 300 has two comparators 30 for one input/terminal 301.
2 and 303, and the response output signal given from the circuit under test 100 (see FIG. 6), which is input to the input terminal 3C), is given to one input terminal of each of the two comparators 302 and 303. Two comparators 302 and 303
DC voltages VOH and VOL that define normal logic levels are applied to the other input terminals of , and the peak value of the pulse of the input response output signal is this DC voltage VOH.

Determine whether or not it exceeds VOL.

In addition, positive polarity DC voltage ■. The comparator 302 to which H is applied is used when the circuit under test 100 operates with a positive logic signal, and is a negative polarity DC voltage. The comparator 303 to which L is applied is used when the circuit under test 100 operates with a negative logic signal.

The example shown in the figure shows a case where positive logic signals are handled.

The logic comparator group 400 includes a logic comparator 401 and a plurality of signal detection circuits 402 and 403 for checking at what timing the output of the logic comparator 401 is generated. This example shows a case where two signal detection circuits 402 and 403 are provided.

The logic comparator 401 can be configured, for example, by an AND gate, and one of its input terminals 404 is given the response output signal output from the level comparator 300, its input terminal 405 is given the expected value signal EXP, and the other one is given the response output signal outputted from the level comparator 300. A signal CPE that controls whether or not to perform logical comparison on two input terminals 406.
give. When all of these human input signals become H logic, the logic comparator 401 outputs an H logic logic judgment output signal.

This logical judgment output signal is output from, for example, a D-type flip-flop (
= Two signal detection circuits 40 that can be configured accordingly
The strobe pulse 5TRB is applied to each data input terminal 2 and 403, and the clock input terminal CKI is applied to the strobe pulse 5TRB.
It is detected whether or not a logic judgment output signal exists at the timing defined by I and 5jRB2.

In addition, 407 and 408 indicate delay elements, and this delay element 4
07.408, the timing is delayed by a time corresponding to the delay time of the logic comparator 401 to match the timing.

Here, the strobe pulses 5TRBI and 5TRB2 are sent to the level comparator 300 (2) through the OR gate 409.
The level comparison output signal is supplied to a comparator 302 constituting a level comparator 300, and outputs a level comparison output signal only during the time when strobe pulses 5TRB1 and 5TRB2 are present. In other words, sense amplifiers are used for comparators 302 and 303, and strobe pulses 5TRBI and 5TRB
The level comparison output signal is output only during the time period 2 is given.

By preparing a plurality of signal presence/absence detection circuits 402 and 403 in this way, it is possible to determine whether the operation of the circuit under test 100 is normal or not, and also to check the response speed distribution of the circuit under test 100 in multiple regions in a single test. It can be classified into

In other words, the generation timing of strobe pulses 5TRBI and 5TRB2 is set to T for the response speed distribution characteristics shown in FIG.
1 and T2, this timing T1 and T2
2, it can be divided into a distribution area A with a fast response, a distribution area B with a normal response speed, and a distribution area C with a slow response. For example, strobe pulses 5TRB1 and 5TR
If the presence of the logic judgment output signal is detected in both B2, it is understood that the circuit under test belongs to the response speed region of region A.

Also, strobe pulse 5TRBI detects no signal,
It can be seen that the strobe pulse 5TRB2 belongs to the normal response speed distribution region B when the presence of the signal is detected.

Furthermore, if no signal is detected for both strobe pulses 5TRBI and 5TRB2, it can be seen that it belongs to region C.

These classifications can be performed by logic signals output from output terminals 411 and 412.

[Problem to be solved by the first invention of this application] In the structure shown in FIG.
and 5TRB2 are superimposed by the OR gate 409, converted into one time series signal, and this time series signal is sent to the comparator 302.
．． It is given to 303.

For this purpose, two strobe pulses 5TRBI and 5TRB
The virtual field in which 2 can be approached is 10 nanoseconds or more depending on the circuit structure of the OR gate 409, etc., and if they are brought closer than this, the strobe pulses will be connected to each other and become one pulse. Therefore, the rise and fall of the response output signal cannot be detected between the strobe pulses. - Recent memory devices have become faster, and some devices have a rise time (TAA) of about 10 to 25 nanoseconds.

Testing such fast response devices requires testing close to 2-5 nanosecond intervals.

Conventional methods have the disadvantage that the strobe pulses cannot be made close to each other for such a long time. Therefore, there arises the disadvantage that fast response type circuits cannot be classified.

In other words, in the case of a fast response type circuit, if the time required for the rise and fall of a signal is about 10 to 25 nanoseconds, the time difference between strobe pulses 5TRBI and 5TRB2 must be set to about 2 to 5 nanoseconds.

Therefore, depending on the conventional circuit structure, there is a drawback that it is not possible to classify the response speed distribution of a high-speed response type circuit in which the time required for rise and fall is about 10 to 25 nanoseconds in a single test.

"Problem to be solved by the second invention of this application" On the other hand, apart from the test for classifying the response speed distribution, there is a circuit under test 100 that outputs a signal with a cycle shorter than the operating cycle of the test device. If this is the case, the operation of this circuit under test has conventionally been tested using a bin multiplex method.

As shown in FIG.
, , to logic comparators 401A and 401B provided in CH2, and the plurality of logic comparators 401A and 401B perform a logic comparison using expected value signals EXP1 and EXP2 having normal speed. This comparison result is for each channel CH1, CH2.
This method detects the presence or absence of a signal at the timing of strobe pulses 5TRBI and 5TRB2.

According to this bin multiplex method, one test cycle T of the test equipment is obtained from the circuit under test as shown in FIG. 10A.
For example, response signals PA, pB, which change twice in M,
Assuming that pc, pD... are output, these two response output signals, PB, , pc... are applied through the level comparator 300 to the logic comparators 401A, 401B provided for the two channels CH, , CH2. It will be done.

Each logic comparator 401A, 401B has expected value signals EXP, . . . , EXP1□, EXP2. .

EXP2□... is applied, and signals CPEI and CPE2 control whether or not to perform logical comparison to other input terminals.
is given, and the response output signal P is twice the normal speed.
A, PB, PC... and two systems of expected value signals EXP10
．． EXP1□...,,EXP2,.

EXP2□... are separate logical comparators 401A and 40
1B, and the comparison result is sent to the signal detection circuit 402A.
and 402B.

Strobe pulses 5TRB1 and 5TRB2 shown in FIGS. 10B and 10C are applied to the signal detection circuits 402A and 402B, and logic judgment output signals PAA, pcc, P■, etc. shown in 10(8)F are outputted from the output terminal 411A. Output terminal 4
11B to logic judgment output signal PBB shown in FIG. 10G.
, PDD-PFF... are output.

In this way, the logic judgment output signals PAA, pea,
PEE.

. . . and PBB, PDD, PFF, .

(Disadvantages of the Bin Multiplex Method) As shown in Figure 9, this multi-Flennox method uses multiple channels CH and CH2 to convert the response output signal output from one output terminal of the circuit under test into a logic circuit. Since this is a method that performs determination, it has the disadvantage that the number of channels used must be twice the speed of the response output signal. Since it is necessary to provide at least twice the number of channels as the number of output terminals of the circuit under test, the scale of the equipment becomes larger1), which has the disadvantage of increasing costs. .

"Problem to be Solved by the Third Invention of this Application" Furthermore, for example, when performing memory defect analysis, it may be necessary to classify each memory cell as good or bad when changing test conditions.

For example, by classifying cells that are defective and cells that are good at access time b, and furthermore, among the cells that are good at access time b, cells that are defective and cells that are good at access time c (c<b) are classified. There are cases where it is desired to classify cells that become defective at access time d (d<c) and cells that become good among the cells that become good at access time d (d<c).

When performing such classification, access times b, c,
For example, d: 25 nanoseconds, C: 30 nanoseconds,
If b=35 nanoseconds, the conventional test equipment shown in FIGS. 7 and 9 has strobe pulses 5TRB1 and 5TR
Since it is not possible to make B2 close to 5 nanosecond intervals, each test must be performed once under different test conditions.

Therefore, conventionally, the test must be performed four times as explained below.

(First time) As shown in FIG. 11, the strobe pulses 5TRBI and 5TRB2 applied to the logic comparator 300 are each set at a timing position of 35 nanoseconds as a test condition, and a test is performed under the conditions. Under these test conditions, the location of the defective cell is stored in the storage area 600A of the defect analysis memory 600.

(Second time) As shown in FIG. 12, strobe pulses 5TRBI and 5TRB2 applied to the logic comparator 300 are set at a timing position of 30 nanoseconds as test condition C, and a test under condition C is performed. As a result of this test, the locations of cells that become defective under test condition C are stored in storage area 600B of defect analysis memory 600.

(Third time) As shown in FIG. 13, strobe pulses 5TRBI and 5TRB2 applied to the logic comparator 300 are set at a timing position of 30 nanoseconds as test condition C, and a test under condition C is performed. At this time, the storage area 60 of the failure analysis memory 600
Read out the position of the cell that has already failed under the test conditions stored in 0A, and prohibit (mask) logical comparison at that cell position. The location of storage area 600 of failure analysis memory 600
Store in C.

(Fourth time) As shown in FIG. 14, strobe pulses 5TRB1 and 5TRB2 applied to the logic comparator 300 are set at a timing position of 25 nanoseconds as test condition d, and a test under condition d is performed. At this time, the storage area 60 of the failure analysis memory 600
The position of the cell that became defective under test condition C is read from 0B, the position information of this defective cell is given to the logic comparator 300 as a mask signal, and the cell that becomes defective under test condition C is excluded from the test object. Perform the test under condition d. At this time, the location of the defective cell is stored in the storage area 600D of the defect analysis memory 600.

In this way, by conducting the tests under conditions c and d four times, the storage area 600 C of the failure analysis memory 600 is
It is possible to obtain the location information of the cells that have become defective under test condition C among the cells that have already passed under test condition C, and the cells that have passed under test condition C can be stored in the storage area 600D of the failure analysis memory 600. It is possible to obtain the location information of cells that are defective under test condition d.

In this way, conventionally, when classifying the access time of a fast-response type memory, each test condition b, c.

This method has the disadvantage that the test takes a long time because the test must be performed every d.

A third object of this application is to provide a circuit testing device that can perform tests in a short period of time even under a wide variety of test conditions.

"Means for Solving Problems" In the first invention of this application, a test signal is applied to a circuit under test, the response output signal is compared with an expected value signal, and a coincidence or mismatch is detected to determine whether the circuit is good or not. In a circuit testing device for determining A circuit testing device is constituted by a plurality of logic comparators that receive a signal detected by a detection circuit, logically compare it with an expected value signal, and determine whether the signal matches or does not match the expected value.

According to the first invention, a plurality of signal extraction circuits are provided, and the plurality of signal extraction circuits are configured to apply strobe pulses through independent signal paths and take out response output signals at different timings. The time difference between the applied strobe pulses can be approached to an extremely small time difference. Therefore, even when testing a high-speed response type circuit, the timings of the strobe pulses can be made close to each other, so that differences in response time can be classified into small time differences in each signal extraction circuit.

As a result, even in a high-speed response type circuit, the difference in response time can be classified into i number of categories (two categories) in a single test.

The second invention of this application provides a circuit testing device that applies a test signal to a circuit under test, compares the response output signal with an expected value signal, and detects coincidence or mismatch to determine the quality of the circuit. A plurality of signal detection circuits that output response output signals from the circuit, a plurality of signal paths that separately apply strobe pulses to the plurality of signal detection circuits, and signals extracted from the separately provided signal detection circuits. A circuit testing device is constructed of a plurality of logic comparators that compare the logic comparators with an expected value signal, and a switching circuit that sets the expected value signal to be given to each of the plurality of logic comparators.

According to the configuration of the second invention, a plurality of stages of logic comparators are provided separately in one response output signal system, and expected value signals can be given to the plurality of logic comparators separately. The period of the response output signal from the circuit is 1 of the circuit test equipment.
Even if a signal with a cycle that is an integer fraction of the test cycle is output, logic comparison can be performed separately for each cycle of the response output signal using a plurality of logic circuits.

Therefore, the circuit under test can be tested at a speed several times faster than the operating speed of the circuit testing apparatus without using the conventional pin multiplex method.

A third invention of this application provides a circuit testing device that applies a test signal to a circuit under test, compares the response output signal with an expected value signal, and detects a match to determine the quality of the circuit. A plurality of signal detection circuits that take out response output signals output from the test circuit, a plurality of signal paths that separately provide independent strobe pulses to the plurality of signal detection circuits, and a plurality of signal paths that are provided separately and that are taken out from the signal detection circuit. A circuit testing device is constructed of a plurality of logical comparators that compare a signal obtained by a signal with an expected value signal, and a signal switching circuit that sets mask data to be applied to each of the plurality of logical comparators.

According to the configuration of the third aspect of the invention, the response speed of a circuit such as a high-speed response memory can be classified into a plurality of categories with good resolution. In addition, since mask data can be given separately from failure analysis memories provided separately, test results regarding a plurality of test conditions can be obtained in a single test.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In the figure, 300 indicates a level comparator, and a response output signal is given to an input terminal 301 from a circuit under test (not particularly shown), and whether the H logic level and L logic level of the response output signal are at normal levels. Compare and judge whether or not.

The level-determined response output signal is applied to a logic comparator group 400. In this logical comparator group 400, expected value data EXP, , EXP2 . It is compared with EXP3... and a match or mismatch is detected.

In the first invention of this application, a plurality of signal detection circuits 402 and 403 and a plurality of logic comparators 401A and 401B are provided in each channel CHl-CHz, CH3, . . . of a logic comparator group 400, and a plurality of signal detection circuit 402
and 403, the presence or absence of a response output signal is determined by strobe pulses 5TRB1 and 5TRB2 sent through separate transmission lines 415 and 416, and the determination result is further outputted to logic comparators 402A and 402B as expected value signals EXP, , F.
:Compared with XP2.

In this example, the signal detection circuits 402 and 403 include sense amplifiers 402A and 403A and a D-type flip-flop 402B.
and 403B. In other words, sense amplifier 402A.

Each output terminal of 403A is connected to a D-type Furinoff"
Strobe pulse 5T is connected to the data input terminals of sense amplifiers 402A and 403B through separate signal paths 415 and 416 to each strobe input terminal of sense amplifiers 402A and 403B.
Supply RBI and 5TRB2. At the same time as this, strobe pulses 5TRB 1 and 5TRB2 are applied to each clock input terminal of D-type flip-flops 402B and 403B. Indicates the case where T.

Each output terminal of the D-type flip flops 1402B and 403B is given to one input terminal of an AND circuit constituting the logic comparators 401A and 401B.
Logic comparator 4 n I provided in CI (2, CH3...
A, 40], and the other input terminal of the AND circuit configuring B are connected to each channel CH1, CH2, C
Expected value signals EXP, , EXP2 ., given from input terminals 405 of H3 . EXP3, . . . are supplied, and it is determined whether each response output signal matches the expected value signals EXP, EXP2, EXP3, .

In the second invention of this application, a signal switching circuit 417 is provided for the logic comparator 401B provided in at least two channels, for example, CH1 and CH2, and this switching circuit 417 allows one logic comparator 40 provided in the two channels to
The present invention is characterized in that it is configured such that the expected value signal to be given to 1B can be selected from either EXP or EXP2.

In other words, by providing the signal switching circuit 417, the logical comparators 401A and 401 of one channel CH1 and the other channel
A state is set in which the expected value signal EX Pl is given to the logical comparator 401B, and a state is set in which the expected value signal EX P is given to the logical comparator 401A of -10,000, and the expected value signal EX P2 is given to the other logical comparator 401B. be able to. Also channel CH
It is possible to set a state in which the expected value signal EXP2 is given to the second logic comparator 401A and 401B, and a state in which the expected value signal EXP2 is given to the logic comparator 401A and the expected value signal EXP1 is given to the logic comparator 401B.

In the third invention of this application, each channel CH.

A plurality of logical comparators 401A provided in CH2...

401B is provided with a mask data switching circuit 418 so that the mask data read from the failure analysis memory 600 can be supplied to any logical comparator.

In other words, the failure analysis memory 600 has multiple storage areas 600.
A, 600B, 600C, and 600D, which logical comparator 401A receives mask data read from these plurality of storage areas 600A to 600D.

Mask data switching circuit 4 for setting whether to give data to 401B
18 will be provided.

Therefore, by providing this mask data switching circuit 418, a plurality of storage areas 6008 to 6008 of the failure analysis memory 600 are provided.
The mask data read from 600D is transferred to each channel C.
Logic comparator 401 provided in H1, CH2, CH3...
It is possible to select which of A and 4nlB to apply the signal to and set the selected state.

Note that 419 and 420 indicate similar signal switching circuits. This signal switching circuit 419.420 has terminals 421°422.4
23. Signals CPEI and CPE2 that determine whether or not to make a logic judgment given to 424.

Select CPE3 and CPE4 and gate 425°426
A case is shown in which the configuration can be set to a state in which both logical comparators 401A and 401B perform logical determination, and a state in which either one of them performs logical determination, depending on the necessity.

According to the first invention of this application mentioned above, the signal detection circuit 4
Since the structure is such that independent strobe pulses STRB1 and 5TRB2 are provided to 02 and 403 through separate signal paths 415 and 416, the signal detection circuits 402 and 403 can be synchronized even if the time difference between the timings of strobe pulses 5TRBI and 5TRB2 is made close. It is possible to detect the rise or fall of the response output signal of the circuit under test within an extremely short time difference without interfering with the circuit under test.

Therefore, as shown in Fig. 2, even if the response signal of a fast response circuit takes about 10 nanoseconds to rise, if the time difference between strobe pulses 5TRBI and 5TRB2 is set to about 5 nanoseconds, the presence or absence of a rise can be detected with high resolution. can do.

As a result, the response speed of a high-speed response circuit can be classified with good resolution by a -degree test.

Further, according to the second invention of this application, the expected value signal EXP,
, EXP2 can be supplied to either of the logical comparators 4nlA and 401B provided in the two channels CH1 and CH2, so the two strobe pulses 5TRBI
The signals detected by 5TRB2 and 401A are
01B can be compared separately.

Therefore, for example, as shown in FIG. 3, even if the period Ts of the response signal output from the circuit under test is 1/2 of one test cycle TM of the test equipment, each data pA, pB
, Presence or absence of PC...! Stroop pulses 5TRBI and 5TRB2 are detected alternately, and the detected signal FAA
, pcc ” ” ” and PBB , PDD ” ”
” (see Figure 3, E) can be logically compared by the logic comparators 401A and 401B separately, so this is essentially equivalent to operating the circuit test device at twice the speed.

According to the conventional multiplex system that realizes this double-speed operation, logical comparators provided in two channels are used to logically compare one response output signal, but in the second invention of this application, one Two signal detection circuits and two logic comparators are provided in each channel, and two signal detection circuits 402 and 403 are provided with independent strobe pulses 5TRB.
Since it is only necessary to configure the test apparatus so that the signal is detected by I and 5TRB2, high-speed tests can be performed without increasing the circuit size of the entire test apparatus.

According to the third invention of this application, each channel CH1, C
Two logic comparators 401 each for H2, CH3...
A and 401B are provided, and these two logical comparators 401A
, 401B can be selectively provided with mask data read from a plurality of storage areas 600A to 600D, making it possible to perform a plurality of classifications in one test.

In other words, as explained in the problem to be solved by the third invention, in the past, it was necessary to perform the test four times to classify memory cells that were defective under each of the test conditions (i), (c), and (d).
According to the third invention of this application, the same classification can be performed in two tests.

The reason for this will be explained below.

Each channel CH1, CH2, CH3... has two signal detection circuits 402, 403 and two logic comparators 40.
1A and 401B are provided, and the mask data switching circuit 41
8, these two logical comparators 401A, 401B
Mask data stored separately can be given to the .

As a result, in the first test, as shown in FIG. 4, the signal detection circuit 402 side was tested with test condition A by setting the strobe pulse 5TRBI timing, and the signal detection circuit 403 side was tested with test condition C. The test can be carried out by

This test result is stored in the storage area 600 of the failure analysis memory 600.
It can be stored in A and 600B.

In the second test, as shown in FIG. 5, the conditions stored in the storage area 600A of the failure analysis memory 600 are read out as mask data for the positions of memory cells that have become defective, and this mask data is transferred to the mask data switching circuit 418. The signal is applied to the logic comparator 401A through the logic comparator 401A.

Along with this, a strobe pulse 5TRB is applied to the signal detection circuit 402 provided in the preceding stage of this logic comparator 401A.
Test conditions C are set by selecting the timing of I.

Also, a strobe pulse 5T given to the signal detection circuit 403
Selection of the timing of RB2 (set up the test condition d, and apply the signal detected under this test condition d to the logic comparator 401
Give to B. Storage area 600B for logical comparator 401B
The position data of the cell that became defective under the test condition C stored in
Give to 1B.

In this way, the two logical comparators 401A and 401B apply condition C and condition d-4 in parallel, and the storage area 600
Testing can be performed while masking with data read from A and 600B.

The test results are stored in the storage area 600 of the failure analysis memory 600.
Store in C and 600D.

The data stored in the storage area 600 (:l:@) in this way is data of a cell that became defective under test condition C among the memory cells that were already good under test conditions.

In addition, the data imported into the storage area 600D is under test condition C.
Among the memory cells that were good under test condition d, data on cells that were defective under test condition d is shown.

Therefore, the memory area 600A stores the data of the memory cell position that has become defective under the test conditions, and the memory area 600B
Since the data of the memory cell position which became defective under test condition C is stored in , four types of classification can be performed by two tests.

"Effects of the Invention" As explained above, according to the first invention of this application, each channel is provided with a plurality of signal detection circuits 402 and 403,
Since the strobe pulses 5TRB1 and 5TRB2 are separately supplied to the plurality of signal detection circuits 402 and 403 through the strobe pulse supply paths 415 and 416 provided separately, the strobe pulses 5TRBI and 5TR are
The presence or absence of a signal can be detected by making the time interval of B2 close to zero. Therefore, the timing of the rise of a response output with a steep rise output from a high-speed response type circuit can be detected with high resolution, and the distribution of response speed can be classified into a plurality of categories by a -degree test.

Furthermore, according to the second invention of this application, the signal detection circuit 402
and 4°03 are mutually independent strobe pulses 5TRB.
In addition to operating with 1 and 5TRB2, the detection signals output from the two signal detection circuits 402 and 403 are logically compared separately by two logic comparators, and the signal is switched to both of these two logic comparators. Expected value signal EXPI through circuit 417.

EXP2 can be given separately.

As a result, even if the circuit under test outputs a response signal with twice the frequency of the test cycle of the test equipment in the above-described embodiment, the signal detection circuit 402 receives two response outputs within one test cycle. It is possible to separately (=detect) at 403 and logically compare the detection results using logical comparators 401A and 401B.

Therefore, the test can be performed at twice the speed without using a two-channel logical comparator like a pin multiplexer, and the time required for the test can be shortened.

Furthermore, according to the third invention of this application, the signal switching circuit 418
The mask data read from the storage area of the failure analysis memory 600 by the two logic comparators 401A and 401B
Since mask data can be selectively applied to any of the above, mask data can be applied to a desired logic comparator according to each test condition.

Therefore, since mask data can be separately given to the two logic comparators in each channel, classification can be performed by applying two test conditions in one test. Therefore, this third invention also has the advantage of shortening the test time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining in detail the first invention of this application, and FIG. 3 is a detailed diagram of the second invention of this application. 4 and 5 are block diagrams for explaining in detail the third invention of this application, and FIG. 6 is a block diagram for explaining the overall configuration of the circuit testing device. , FIG. 7 is a block diagram for explaining the configuration of a conventional circuit testing device, FIG. 8 is a graph for explaining the classification method of circuits under test in the circuit testing device, and FIG. 9 is a conventional circuit testing device. Figure 10 is a waveform diagram to explain the operation of the multiplex method, and Figures 11 to 14 show the operating characteristics of the circuit under test using a conventional circuit test device. FIG. 2 is a block diagram for explaining a method of classifying. Patent applicant: Atopantest Co., Ltd. Agent
Person Kusano Takusai 5 Zuhe Figure 8 > Figure 10 Figure 11

Claims (3)

[Claims] (1) A. In a circuit testing device that applies a test signal to the circuit under test, compares the response output signal with an expected value signal, and detects the coincidence or inconsistency to determine the acceptability of the circuit. B. Provided in each channel. C. A plurality of independent signal paths that respectively apply strobe pulses to the plurality of signal detection circuits, and D. Signals detected by the plurality of signal detection circuits. A circuit testing device comprising: a plurality of logical comparators for performing logical comparison with a given expected value signal and determining whether the expected value matches or does not match the expected value. (2) A. In a circuit testing device that applies a test signal to the circuit under test, compares the response output signal with an expected value signal, and detects a match or mismatch to determine the acceptability of the circuit. B. From the circuit under test. A plurality of signal detection circuits for extracting response output signals to be output; C. A plurality of signal paths for respectively providing independent strobe pulses to the plurality of signal detection circuits; D. Extraction from the separately provided signal detection circuits. A circuit testing device comprising: a plurality of logical comparators for comparing a signal to be applied to an expected value signal with an expected value signal; and a signal switching circuit for selecting an expected value signal to be applied to each of the plurality of logical comparators. (3) A. In a circuit testing device that applies a test signal to the circuit under test, compares the response output signal with an expected value signal, and detects a match or mismatch to determine the acceptability of the circuit. B. From the circuit under test. A plurality of signal detection circuits that take out response output signals to be output; C. A plurality of signal transmission lines that separately provide independent strobe pulses to the plurality of signal detection circuits; D. From the separately provided signal detection circuits. A circuit testing device comprising: a plurality of logical comparators for comparing a signal to be extracted with an expected value signal; and a mask data switching circuit for selecting mask data to be applied to each of the plurality of logical comparators.