JPH04118678U - Logical comparison device for IC test equipment - Google Patents

Abstract

(57) [Summary] [Purpose] To shorten the test time for IC elements whose output changes during one test cycle. [Structure] The output of one pin of the IC element under test is compared with a reference high level and a reference low level in level comparators 12 and 13, respectively, and these comparison outputs are sent to blocks 31 and 32.
are supplied to both. Blocks 31 and 32 are not shown in the figure, but have the same configuration, and the outputs of level comparators 12 and 13 are taken into a timing comparator using a strobe, and the outputs are each an expected value with a period of one test cycle. be compared. Block 31,3
The two strobes ST1 and ST2 are generated at different timings for each test cycle.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This idea is based on the ability to set the output of an IC device under test in IC test equipment. The output is captured using a timing strobe, and the captured output is logically compared with the expected value. The present invention relates to a logic comparison device that determines whether an IC device under test is a good product or a defective product.

0002

[Conventional technology]

FIG. 3 shows a conventional logical comparison device. Connect one pin of the IC device under test to input terminal 11. The level comparators 12 and 13 each output a reference high level VH. , and the reference low level VL, and the level comparator 12 inputs the reference high level VH. outputs a high level when the reference high level VH is lower, and outputs a low level when it is higher than the reference high level VH. and the level comparator 13 outputs a high level when the input is higher than the reference high level VL. and outputs a low level if it is lower than the reference low level VL.

0003 Each output of these level comparators 12 and 13 is connected to a timing comparator 1. 4 and 15, it is taken in by the strobe ST, that is, it is sampled and held. Ta The output of the timing comparator 14 is supplied to logic comparison circuits 16 and 17, and , are supplied to the OR circuit 19 through the inverter 18. timing comparator The output of 15 is supplied to logic comparison circuits 21 and 22, and also passes through an inverter 23. The signal is then supplied to the OR circuit 19 and the logic comparison circuit 24. The output of the OR circuit 19 is The signal is supplied to the physical comparison circuit 25. Logic comparison circuits 16, 17, 21, 22, 24, 2 5 is a case in which each of the circuits is constituted by an AND circuit.

0004 The high level expected value EH is input to the logic comparison circuits 16, 17, 24, and 25, and the logic The inverted signal *EH of the high level expected value is input to the comparison circuits 21 and 22, and the logical comparison circuit The low level expected value EL is input to the paths 21, 22, 24, and 25, and the logic comparison circuit 16 , 17, an inverted signal *EL of a low level expected value is input. Logic comparison circuit 16, 2 The output of 1 is supplied to the OR circuit 26 and also to the OR circuit 27. logical ratio The outputs of the comparator circuits 17, 22, and 24 are supplied to an OR circuit 28. Logical comparison circuit 25 The output of is supplied to OR circuits 27 and 29.

[0005] If the input is below VH when the expected value is at a high level, each of the logic comparison circuits 16 and 17 When the output is “1” and the expected value is low level, if the input is above VL, the logical ratio Each output of the comparator circuits 21 and 22 becomes "1". The expected value is high impedance, i.e. , when the expected value is high level and low level at the same time, the input is above VH and V If it is below VL, the output of the logic comparison circuit 25 becomes "1", and the input is below VL. Then, the output of the logic comparison circuit 24 becomes "1". For states other than the above, the logic comparison circuit 16 , 17, 21, 22, 24, and 25 are "0".

[0006] Therefore, if a discrepancy with the expected value occurs from the OR circuit 27, the previous IC element under test is defective. A defective signal FMF indicating that this is the case is output. The output of the IC element under test is high level. OR circuit 28 When a failure occurs, the output of is determined in which of the two states other than the expected value the failure occurred. This is a signal FMC indicating whether Set the strobe ST at an appropriate time during each test cycle. The IC device under test was being tested to see if it operated normally.

[0007]

[Problem that the idea aims to solve]

In normal operation, the output of one pin of the IC device under test will last for one test cycle. Some things change along the way. In such cases, the expected value changes with each test cycle. Conventionally, it can only be performed at normal times during the test cycle. Separate tests were conducted on the anterior and posterior parts of the change point. In other words, conventionally In this case, it is necessary to run the test pattern twice and perform the test twice, and that is all. The exam took a long time.

[0008]

[Means to solve the problem]

According to this idea, the output from one pin of the IC element under test can be tied as before. The strobe data is input to the timing comparator for each test cycle, and the expected value and At the same time, the outputs of the same pins of the IC device under test are compared using a physical comparison circuit. At each strike cycle, other sensors are activated using a strobe with a timing different from the above strobe. input into a timing comparator and compare its output with other expected values using another logic comparison circuit. It is made to compare.

[0009]

【Example】

FIG. 1 shows an embodiment of this invention, and parts corresponding to those in FIG. 3 are given the same reference numerals. . Of the parts shown in Figure 3, the input side of the timing comparators 14 and 15 is The output side of the circuits 26 to 29 is shown in block 31, and strobes, expected values, and Each force signal is given the same code plus the number 1. In this example, the block A block 32 having the same configuration as the block 31 is provided, and includes level comparators 12 and 13. are also provided to block 32. Timing comparator in block 32 The strobe ST2 supplied by the strobe ST1, but the timing is shifted from strobe ST1. Block 32 also has a high level expected value EH2, its inverted signal *EH2, and a low level expected value EL. 2. The inverted signal *EL2 is input and the same operation as in FIG. 3 is performed.

0010 Outputs FMF1 and FMF2 from blocks 31 and 32 indicating whether or not each is defective are selectable. is supplied to the A and B inputs of the The outputs FMC1 and FMC2 indicating the Supplied. The output of the selector 34 and the output FMF2 of the block 32 are It is supplied to the A and B inputs of the collector 35. The selectors 33 and 34 receive the same control signal S. C1, and the selector 35 is controlled by a control signal SC2. Selector 33~ 35 outputs A input when the control signal is “0” and outputs B input when the control signal is “1”. do. In addition, the output TFL1 and TFL2 are high, indicating each level of failure in blocks 31 and 32. Outputs TFZ1 and TFZ2 indicating impedance failure are supplied to the OR circuit 36. There is.

[0011] According to this configuration, the timing when the output should change normally in the middle of the test cycle Generate strobes ST1 and ST2 before and after, and ensure that the output is normal. Each expected value EH1, EL1, EH2 before and after the timing to change , EL2 are generated at each test cycle period, so that one test can be performed in one test. Tests can be performed for varying outputs during a power cycle. In this case, By selecting FMF1 with the selector 33 and FMF2 with the selector 35, These can be stored separately in the fail memory as needed. Or times If “1” occurs even once in the output of the circuit 36, the IC element under test can be determined to be defective. Ru.

0012 Regarding block 32, the mode selection signal MOD is set to "0" to make it inactive. , the signal MOD can be set to "1" to be in the operating state, and this signal MOD can be set to For example, if input to logic comparison circuits 16, 17, 21, 22, 24, 25 in FIG. good. If the A input is selectively outputted to the selectors 33, 34, and 35, FM F1, FMC1 can be output, signal MOD is set to "1", and corresponding to selectors 33 and 34. The B input is selectively output, and the A input is selectively output to the selector 35. For example, FMF2 and FMC2 can be output.

[0013] In the past, 3 bits per pin of the IC device under test were processed in one test cycle. Use the cut pattern data and decode it to create the drive waveform and expected value. However, in the case of Figure 1, 3 bits of pattern data A are similarly generated in each test cycle. , B, and C, the mode selection signal MOD is “0” and “1” in FIGS. 2A and B. It is sufficient to use a decoder that satisfies the logic value table as shown. In these, ELi (i = 1, 2) is “1”, EHi is “0”, the expected value is low level, and ELi is “0”, E When Hi is “1”, the expected value is at a high level, and when ELi and EHi are both “0”, it is always in good condition. When ELi and EHi are both “1”, the expected value indicates a high impedance state. vinegar. In addition, in FIG. 3, EL1 and EH2 of FIG. 2A were used.

[0014]

[Effect of the idea]

As mentioned above, according to this invention, the timing comparator and logic comparison circuit can be By providing two sets and operating them with different strobes, the Even for IC elements under test whose output changes, the expected value for each test cycle is used. The test can be completed in one test, cutting the test time in half compared to conventional methods. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention.

FIG. 2 is a diagram showing an example of the relationship between pattern data and expected values.

FIG. 3 is a block diagram showing a conventional logical comparison device.

Claims (1)

[Scope of utility model registration request] 1. A first timing comparator that captures the output of the IC device under test with a first strobe generated in each test cycle, and a first logic that compares the output of the first timing comparator with a first expected value. a comparison circuit,
a second timing comparator that receives the output of the IC device under test with a second strobe that is generated in each test cycle and has a phase different from the first strobe; A logic comparison device for an IC test device, comprising a second logic comparison circuit for comparing the two logic comparison circuits.