JPS59152598A - Test result fetching device - Google Patents

Abstract

PURPOSE:To fetch defects surely, by fetching successively components, which correspond to one cycle of plural registers arranged in parallel, of the test result for every cycle and clearing it one cycle behind at least to generate no blind sectors even if a test rate is higher. CONSTITUTION:A test result 7 which is outputted from a comparator 6, which decides the test result, at a defect occurrence time is formed by a one shot pulse circuit 12 to generate a defect pulse signal 11. Clock signals C1 and C2 generated by a clock circuit 26 fetch the defect pulse signal 11 to flip-flops 20 and 21 alternately in every test cycle through AND gates 221 and 222. NAND between write pulses WSTB1 and WSTB2 and outputs Q1 and Q2 are operated in NAND gates 231 and 232 alternately, and thus, outputs Q1 and Q2 of flip-flops 20 and 21 are stored in defect storage memories 24 and 25 respectively before clearing, and they are cleared just before the defect fetch in the next cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a device for capturing test results used in an IC memory testing device.

[Prior art]

FIG. 1 is a block diagram showing the configuration of an IC memory testing device, in which a pattern generator 1 sequentially and cyclically generates a set of input data 2 and an expected value 3, and supplies the input data 2 to a memory under test 4. The output data 5 of the memory under test 4 and the expected value 3 at that time are compared by a comparator 6, and a defect is determined depending on whether the two match or do not match, and a test result 7 is output. When a mismatch occurs, that is, when a defect occurs, the address 8 from the pattern generator 1 indicating which address of the memory under test 4 has the defect and the test result 7 are transferred via the test result importing device 10. and stored in the memory 9.

FIG. 2 shows a conventional circuit configuration of a loading device 10 for loading test results 7 into a memory 9 in an IC memory testing device such as the above, and FIG. 3 shows its operation time chart. In these figures, the output take 5 of the memory under test 4 and the expected value 3 are compared by the comparator 6 in each test cycle of the test signal TC from the clock circuit 17.
Assume that defective signals F and F3 of test result 7 shown in the figure are generated. In general, the pulse width and time of the defective signal fi is not constant. Temporarily haunted by Frog 16. At the beginning of the next test cycle 2, the flip-flop tube 16 is cleared by the clear signal C'LR synchronized with the test signal TC, and the defective signal from test cycle 2 is then stored. This is repeated sequentially, but the next stage clip-flop 14 is set to the flip-flop 1 of the previous stage.
The defective pulse signal 11 stored in step 3 is the clear signal CLR.
A clock signal generated just before this signal CLR (which is of course synchronized with the test clock TC) before being cleared by CI=K, the signal Q2 (F+
, Fv, Fs), which are held for one cycle. This and the memory write signal 11'STB created by the clock circuit 17 are NAND'ed by the Nant gate 15, and only in the case of a defect (Q2=1), the Nant gate 15 output is 0 and stored in the memory 9. written.

The write address is specified by setting the address signal 8 from the pattern generator 1 shown in FIG. 1 in the address register 16 using the clock signal CLK.

However, according to the conventional method described above, in order to import test results 7 in real time, the results of the test in the previous cycle (
It is necessary to clear the contents of the flip-flop 15 and to take in the defect in that cycle within one test cycle.

For this reason, there is a drawback that it is not possible to take in defects while clearing is being executed in each test cycle, that is, during the pulse width α of the clear signal CLR. In particular, when the test clock TC becomes high-speed, about 20 to 6 oMHz, the pulse width α cannot be reduced unnecessarily due to technical conditions, so the ratio of this dead zone increases. For example, the pulse width of the clear signal CLR is 6 nsec, and the test period is 3
0nsttc,! :Then, a dead zone will occur for 20% of the -cycle, υ, and the failure occurrence time is -
It does not necessarily occur at a specific position within a cycle, and it is not constant depending on the memory being measured, so if it occurs continuously, it will occur at intervals shorter than the time of one cycle. Assuming that the clear pulse r1 is constant,
The proportion occupied by this dead zone tended to be more dog-like.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a test result acquisition device that does not generate a dead zone even when the test rate becomes high and can reliably capture defects.

[Summary of the invention]

The device of the present invention records test results for each test cycle.
It is characterized by sequentially loading one cycle at a time into multiple registers installed in parallel, and clearing each register in a cycle that is delayed by at least one cycle after the register loading cycle. That is.

[Embodiments of the invention]

Hereinafter, the present invention will be explained with reference to the embodiment shown in FIG. 4 and FIG. 5 showing its operation time chart. In this embodiment, in order to simplify the explanation, two registers are used. First, as in the conventional case, the test result 7 outputted from the comparator 6 for determining the test result when a failure occurs is stored in a one-shot register. , ) is shaped by the pulse circuit 12, and a defective pulse signal 11 is generated. Next, in this embodiment, the defective pulse signals 11 are alternately taken into the flip-flops 20 and 21, which serve as two registers. That is, the clock signal Ci,
Generate C2 in the black and white circuit 26,
The defective pulse signal 11 is alternately taken in to the flip-flops 20 and 21 via 221 and 222 every test cycle. The clock signals C1 and C2 used here are test clock signals.
It can be easily created using a binary counter that takes TC as input. 'Furthermore, if the number of separate capture registers is increased, a counter with a step count commensurate with the number may be provided.

In this way, the defective signals F1 to FsrQ1. Q2) is held at least until the end of the next test cycle, and test clock TC and clock signals c1. c.
The clear signal CLR1 in FIG.
Each is cleared by CLR2 immediately before the next cycle's failure is taken in. Therefore, the output Q1 of the free lag flops 20 and 21. Q2 is stored in the cleared prepressure failure storage memories 24 and 25, respectively, but this is also caused by the two-phase write pulses WSTB1. WSTB2 is output from the clock circuit 26, and this and output Q1. 9 is performed by taking Nands with Q2 alternately at Nands gate 251.232. This write pulse WSTB1. WST
B2 is clock c1. A button can be easily created using a signal obtained by appropriately delaying c2, but a clock signal matched to the cycle may be used for separate division. In addition, the address of the memory is stored by inputting the address signal 8 from the pattern generator 1 into the address registers 27 and 28 using the clear signals CLR2 and cLRl, respectively, and accessing each memory 24 and 25. (Note that the address for accessing the memory 24 is the clear signal CLR2 that clears the 7 lip-flop 21 on the memory 25 side, and vice versa for accessing the memory 25). Incidentally, if the defective storage memories 24 and 25 are set to logic 1 or 0 (no defect) in advance, then the test result 7 may be forcibly set to 0 and read into all addresses. Alternatively, separately, the defective memory 24.2
5 can also be initialized by address, data, and write strobe from a dedicated computer (not shown in FIG. 4).

Note that in this embodiment, the number of divisions for capturing is set to two, but this can easily be divided into even more divisions.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, test results can be input alternately through a plurality of registers, and the clearing and transfer to the defective memory can be performed while other registers are being loaded. It is possible to eliminate the dead zone for defective captures, and there is also more time to transfer defective captures to the memory, so the access speed is slower than before, so the transfer operation can be performed reliably, and This has the effect of significantly improving reliability.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the FiIC memory test device, Fig. 2 is a diagram showing a conventional test result import device, and Fig. 6 is a block diagram showing the configuration of the FiIC memory test device.
4 is a timing diagram showing the operation of the apparatus shown in FIG. 2, FIG. 4 is a diagram showing an embodiment of the present invention, and FIG. 5 is a timing diagram showing the operation of the embodiment shown in FIG. 3...Expected value 4...Memory under test 5.
...Output data 6...Comparator 7...Test result 12...One-shot pulse circuit 11...Failure pulse signal 20.21...Lip-flop circuit 221, 222
...AND gate circuits 231, 232...Nant gate circuits 24, 25...Defective storage memory 26...Clock circuit 27, 28...Address register

Claims (1)

[Claims] A defective signal indicating a test result obtained by comparing the correct output pattern of the logic device and the actual output pattern corresponding to the test pattern for each test cycle is sequentially scanned one by one for each test cycle. A plurality of registers for loading into a click, a control function for the above-mentioned cyclic loading into each of the registers, and the contents of each register are cleared during a test cycle for loading into a register other than the register. What is claimed is: 1. A test result importing device comprising a control circuit having a function and a control circuit having a function of transferring the contents of each register to a memory device between the above-mentioned loading and clearing.