JPH03176680A - Testing device for ic - Google Patents

Abstract

PURPOSE:To make a highly efficient test and a fail analysis easy by providing plural quantities of fail memories operated at a rate for RAM and fail memories with the same capacity operated at a rate for SAM. CONSTITUTION:The device is furnished with a detector 5 to detect a transfer cycle between the memory part and shift register part and a RAM address counter 6 provided with a counting function latching the transfer address of memory part. Also plural fail memories 15-A, 15-B operating with the fails generated at the different kinds of rate on the RAM side and SAM side depending on each rate, are furnished. A parallel test at the RAM side and SAM side can be efficiently made in such a manner that a synchronous cycle at the time when data between the RAM part and SAM part are transfered is detected and also the fail information of SAM part is fetched into the address position of fail memory equivalent to the address of RAM part before the time of transfer, thereby the fail analysis after the test is made easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video memory unit (hereinafter referred to as RA) such as a memory for one image.
M) regarding the test device.

[Conventional technology]

In general, a single-image video RAM consists of a RAM section as a memory section and a shift register section (hereinafter referred to as SAM) as a logic section, and the SAM section is mainly composed of a shift register of a predetermined length.

One line of data from the RAM section at an arbitrary row address is transferred to the shift register, and the memory data is read out from the 51M section in response to a high-speed clock signal. The RAM section and SAM section are
Because it can work asynchronously.

During read and write operations of the RAM section, the SAM section is read out at high speed using a read clock different from the test cycle of the RAM section.

As a device for testing this kind of memory, JP-A-62-2
It is described in Publication No. 72165. This uses buffer memory to generate expected values in SAM tests.
Write the same data as the RAM section in advance, and
When reading the part, the expected value pattern of the SAM part is generated by switching to the address according to the counter, which is the read address of this backup memory, and reading it, and the user is not aware of the expected value pattern data of the SAM part. I can take the test.

However, there is no need to discuss the method of storing the results of simultaneous testing of the RAM section and SAM section of the memory under test.

τAlso, what is the test method performed with a conventional memory tester?

The tests of the RAM section and the SAM section are divided into two tests, each test is stored in one fail memory, and a fail analysis process is performed. Alternatively, the successive test results of the RAM section and the SAM section are overwritten and captured in one fail memory.

[Problem to be solved by the invention]

For this reason, when conducting tests in parts, it is necessary to read out the fail information that has been captured twice into the analysis computer for later analysis processing. becomes more difficult and the test time becomes longer.

Furthermore, in the case of overwriting, it is difficult to analyze the test results on the RAM side and the SAM side, and parallel operation tests cannot be performed because there is no simultaneous storage function for simultaneous operation tests of different rates.

An object of the present invention is to provide an IC testing device that facilitates highly efficient testing and failure analysis.

[Means to solve the problem]

The above purpose is to provide a plurality of fail memories of the same capacity that operate at a late rate for RAM and a plurality of fail memories that operate at a rate for SAM, a means for detecting a data transfer cycle between RAM and SIN, and a RAM address before transfer. This is achieved by loading the fail on the SAM side into the fail memory corresponding to the address on the RAM side using the address from a counter that operates in synchronization with the rate on the SAM side.

[For production]

The present invention includes a plurality of fail memories that operate depending on the respective rates to detect failures that occur at different rates on the RAM side and the SAW side, and detects synchronization cycles during data transfer between the RAM section and the SAM section. , by importing the fail information in the SAM section into the fail memory address location equivalent to the address in the RAM section before transfer, the RAM side and S
Parallel testing on the AW side can be performed at a high rate5, and failure analysis after testing can be facilitated.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. RAM/SAM simultaneous operation of video RAM
The test is conducted as follows.

As in the memory under test 4 shown in FIG.
7 in the data transfer cycle shown in Figure 4.
The address indicated by the number address becomes the successive start address of the SAM section, and is read from the SAM section after the transfer cycle. Before and after this transfer cycle, the read operation (or write operation) of the SAM section and the read/write operation of the RAM section can be executed simultaneously asynchronously.
Output DI10, SI/7 when AM section operates simultaneously
The fail processing of the test result is RAM cycle and S
It is necessary to perform parallel processing in accordance with the different rate operations of the AMv cycle.

Moreover, if a failure on the SAM side can be easily corresponded to the RAM address (Xi+Yi>+(,Xi, Yi+I)+-) before transfer, subsequent failure analysis will be very convenient.

Next, a method for realizing one or more functions will be explained with reference to FIG.

The memory under test (denoted as MUT) 4 has x and Y addresses Ad as a test pattern for RAM.
It, memory control signals (6 rows, rows, 11 lights, etc.), memory write data, etc. are sent from a memory pattern generator (referred to as ALPG) 2 to a waveform shaping circuit 3 at a predetermined time and voltage. It is shaped into an amplitude and written to memory.

Further, an expected value pattern for comparison with the read data Dr/δ of the RAM is generated from the ALPC 2, the response time of the RAM and the amount of delay are matched by the delay circuit 17, and the comparator 13
is supplied to the fail memory 15- based on this judgment result.
A or 15-B is arbitrarily switched by multi-break v14 and stored at the same address location as the failed RAM address. The address used in the fail memory at this time is the X, Y address given from the ALPG 2 to the HUT 4, which is supplied to the fail memory 15 by the multiplexer 11 via the delay circuit 17. This R
In the 11M test, the RAM cycles are determined by the timing generator (
Determined by rate 1, which is the output of 1 (denoted as TG),
ALPC; 2 and fail memory 15 operate.

The data transfer cycle from RAM to SAM in FIG.

It is transmitted within this RAM cycle.

The read operation on the P side and the SAM side is performed when the memory under test 4 is
One bit of the control signal of ALPG 2 is assigned to the input clock for M, and the waveform is shaped as a clock pulse and supplied. SAM output sI/'5 is output in synchronization with this clock. The buffer memory 10 has H
The same data as the RAM of UT4 is stored, and this output data is used as an expected value pattern for SAM, and the SAM output is compared with the comparator 12, and the other fail memory FM15 having the same configuration as the fail memory used in the RAM test is
The failure on the SAM side is stored in . SAM at this time
Since the input address of 1M15 used for fail capture on the side corresponds to the RAM address (Xi, Y address) before the transfer, before reading the S, 4M data, the unique address of the data transfer cycle as shown in Figure 4 is set. The cycle is detected by the transfer cycle detector 5, and the SA specified in this cycle is
M read start address Yi and RAM unit transfer low address Xi tj (taken into RAM address counter 6, read address is generated from this address in synchronization with rate 2 of TG1. Rate 2 of TG1 is input clock to HUT A rate with the same period as TG1 is set and created in advance in TG1.

Next, a configuration for detecting the xi and Yi addresses within a transfer cycle and loading them into the address counter 6 to generate an address for the SAM will be described with reference to FIG.

The transfer cycle detector 5 detects the RA of the transfer cycle in FIG.
When DT='L' and WE='H' when S descends,
The Xi address is detected and upon the falling of the C1S signal.

1) When T = 'L', WE = 'H', Y
Since the i-address is detected, a configuration as shown in FIG. 2 is implemented. The selector 21 in FIG. 2 selects the input control signals (RAS, CAS, I) T/□z, WE assigned to the NUT from among the control signal rubits of the ALPG 2 arbitrarily assigned during the test of the HUT 4.
) is selected and specified in advance. From these signals, the selection gate 22 detects the Xi address based on the conditions when the RAS falls, and similarly, the selection gate 22 detects the Yi address when the above-mentioned conditions occur when the CAS falls.

These signals cx detected by the transfer cycle detector 5,
cy serves as a control signal for loading the X at L/s from the ALPG into the RAM address counter x7 and the Y address into the RAM address counter Y8. When this load signal is output, T
When the rate 2 from Gl is input as a clock, the X and Y addresses are latched in each counter 7.8, and the currant operation is started with the subsequent clock, and the addresses are incremented. At this time, the mode such as the increment operation of the counters 7 and 8 is individually designated by the setter 23, and in this case, the mode of the increment operation of the counter 7.
Only the 8th side is incremented, and the counter X7 is not incremented while holding the value loaded with the X address.

The expected value in the SAM test may be generated from the buffer memory 10 in FIG.
It is read by the Y address and compared with the output data on the SAM side by the comparator 12.

In addition, 1M15-A and 15-B can simultaneously capture failures on the RAM and SAM sides during test, and can be input through the multiplexer 11 as the address from the failure analysis channel 16 for analysis after the test, so they can be input simultaneously or independently. Can perform failure analysis.

The RAM test and SAM test have been explained separately above.

In the case of the simultaneous operation test of SIN read and RAM read/write after transfer as shown in FIG. 3, since each rate of TG1 can operate independently, a parallel test is of course performed.

〔Effect of the invention〕

According to the present invention, RAM fail and SAM fail that occur during different rate operations can be stored separately, and S, 1M fail can be stored in RAM before transfer from RAM.
Since it is stored in the fail memory corresponding to the M address, subsequent failure analysis is very easy.

[Brief explanation of drawings]

FIG. 1 is a system diagram of an embodiment of the present invention, FIG. 2 is a system diagram of a RAM address detection section of the embodiment of the present invention, and FIG. 3 is an explanatory diagram showing the configuration of a video RAM. FIG. 4 is an operation timing chart of test waveforms applied to the memory under test. 1 ・・・・・・°・・・・・・・・・・・・・・・
・・２ ・・・・・・・・・・・・－・・・・・・・・・・
・・・・３ ・・・・・・・・・・・・・・・・・・
・・・・・・4 ・・・・・・・・・・・・・・・・・・
・・・・・・・・・5 ・・・・・・・・・・・・・・・
・・・・・・・・・6 ・・・・・・−・・−・・・・・・
・・・－・・・・・・7 ・・・・・・・・・・・・・・・
・・・・・・・・・・・・8 ・・・・・・・・・・・・
・・・・・・・・・・・・10 ・・・・・・・・・・・・
−・・・・・・・・・・・・11 ・・・・・・・・・・・・
・・・・・・・・・・・・・・・12.15 ・・・・・・
・・・・・・・・・・・・15-. 4.15-B ・・・ 16 ・・・・・・・・・・・・・・・・・・・・・・・
17 ・・・・・・・・・・・・・・・−・Axis・・・・・
14.18.19 ・・・・・・・・・21 ・・・
・・・・・・・・・・・・・・・－・・・・・・22...
・・・・・・・・・・・・・River・・・・・・23 ・・・
・・・・・・・・・−・・・・・・・・・・・・ Timing generator Memory pattern generator Waveform shaping circuit Memory under test Transfer cycle detector RAM address counter RAM address counter X RAM address counter Y Buffer Memory multiplexer comparator fail memory failure analyzer delay circuit multiplexer selector selection gate setter Figure 5 Punishment Figure 4

Claims (1)

[Claims] 1. In a test device for multi-board memory such as semiconductor memory, means for detecting a transfer cycle between a memory section and a shift register section, and a counting function for latching transfer addresses of the memory section. a first fail memory that operates with the address, stores the fail on the shift register side, and a second fail memory that operates with the address from the pattern generator stores the fail on the memory side. 1. An IC testing device characterized by comprising an individual storage means for storing failure information. 2. The fail memory is composed of multiple sets of memories with a capacity equal to or higher than that of the memory section side, and is used in common to capture the fail on the memory section side and the shift register section side, and the fail memory on the shift register side side is An IC testing device characterized by comprising means for storing in an address position of a fail memory corresponding to the memory unit address before transfer. 3. In simultaneous testing of the memory section and the shift register section, the fail information taken into the first and second fail memories is tested simultaneously using an external or computer readout address, or I is characterized in that failures before and after transfer can be analyzed by reading them individually.
C test equipment.