JP3424715B2 - Semiconductor test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus, and more particularly, to efficiently transferring test pattern generation data stored in a test pattern generation data file to a test pattern generator. The present invention relates to a semiconductor test apparatus. 2. Description of the Related Art A semiconductor test apparatus having a test pattern generator will be briefly described with reference to FIG. The semiconductor test device shown in FIG. 3 is a semiconductor memory test device, which comprises a timing generator 10, a test pattern generator 20, a waveform shaper 30, and a logical comparator 40.
The test pattern generator 20 outputs an address ADS to be given to the memory under test M, test pattern data TPD, and a control signal CS according to a reference clock CK generated by the timing generator 10. Each of these data is supplied to a waveform shaper 30, where it is shaped into a waveform required for a test. Data applied from the waveform shaper 30 to the memory under test M is temporarily stored here. The memory M under test stores the test pattern data TP by the control signal CS.
D writing and reading are controlled. The read data RD read from the memory under test M is given to the logical comparator 40, where the expected value data ED output from the test pattern generator 20 and the read data RD are compared. The quality of the memory under test M is determined. FIG. 4 shows a configuration of a test pattern generator 20 of a semiconductor test apparatus. FIG. 5 is an operation timing chart thereof. In addition to the timing generator 10, the test pattern generator 20 is further connected to a control device of a semiconductor test device composed of a computer or a test pattern data transfer device 50. Here, first, the test pattern data PAD is transferred from the control device of the semiconductor test device or the test pattern data transfer device 50 to the test pattern generator 20 and is supplied and stored in the PAD storage unit 2. When the address identification signal AE and the test pattern data are fetched and stored in the PAD storage unit 2, a STATUS signal indicating the storage is sent from the PAD storage unit 2 to the PAD storage unit read control unit 3. The PAD storage unit read control unit 3 sends a READ signal to the PAD storage unit 2 based on the STATUS signal, and
From the address identification signal AE and the test pattern data A
The DA is extracted and input to the test pattern data storage address control unit 4 and the test pattern data register 5. The test pattern data Dn in the address identification signal AE and the test pattern data ADA include channel information of the semiconductor test device, write control information for the test pattern data storage unit 6, address information and write control information for the test pattern generator 20, and so on. include. Here, when the time relationship between the PAD signal and the ADA signal is as shown in the time chart of FIG. 5, the ADA signal data has a temporal relationship. Will be present in the gap. In this case, the time gap corresponds to almost one half of the time for transferring the ADA signal data, and the transfer speed is degraded by the delay. [0005] The present invention provides a semiconductor test apparatus which efficiently transfers test pattern generation data stored in a test pattern generation data file which solves the above-mentioned problem to a test pattern generator. Means for Solving the Problems A timing generator 10,
The test pattern generator 20 includes a test pattern generator 20, a waveform shaper 30, and a logical comparator 40. The test pattern generator 20 supplies an address ADS and test pattern data TPD to the memory under test M according to a reference clock CK generated by the timing generator 10. , A control signal CS, and these data are supplied to the waveform shaper 30 to be shaped into waveforms necessary for the test. The memory under test M is controlled by the control signal CS to write and read the test pattern data TPD.
The read data RD read from the memory under test M is given to a logical comparator 40, which compares the expected value data ED output from the test pattern generator 20 with the read data RD. On the other hand, in a semiconductor test apparatus including a test pattern data PAD and a test pattern data transfer device 50 for transferring an address identification signal AE for identifying whether a signal in the test pattern data PAD is an address signal or a data signal, The test pattern generator 20 has a PAD storage unit 2 for storing the test pattern data PAD and the address identification signal AE and transmitting a STATUS signal in response to the test pattern data PAD. Read PAD storage unit that sends READ signal to storage unit 2 A control unit 3, and wherein, PAD
The address identification signal AE and the test pattern data ADA are read from the storage unit 2 in response to the READ signal, and the multiplexer 8 that inputs and switches and outputs the address signal ADRS and the test pattern data ADA is provided. An address latch 7 for taking in the address identification signal AE when active and outputting the address signal ADRS to the multiplexer 8 is provided. When the address identification signal AE1 is inactive, a signal / AE1 indicating a data cycle and a READ signal And an AND gate 9 for outputting a signal obtained by taking an AND between them to the multiplexer 8 as a selection signal DSA. The multiplexer 8 outputs every other address signal A1 when the signal is 0 according to the selection signal DSA. When this is 1, the data signal D1 to output the D5, and a semiconductor testing device and has a pattern data storage unit 6 for storing the signal output from the multiplexer 8. An embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. FIG. 1 is a diagram for explaining an embodiment, and FIG. 2 is a time chart. The test pattern generator 20 is connected to a control device of a semiconductor test device composed of a computer or a test pattern data transfer device 50. The test pattern data PAD is sent from the test pattern data transfer device 50 to the test pattern generator 20, and is supplied and stored in the PAD storage unit 2. Then, the test pattern data transfer device 50 further stores the test pattern data PA in each transmission cycle to the PAD storage unit 2.
An address identification signal AE for identifying whether the signal at D is an address signal or a data signal is also transmitted and stored. One cycle of the PAD signal is composed of one of the first address signals An and a plurality of data signals Dn successively subordinate thereto. That is, as shown in the time chart of FIG. 2, one address signal A1 is transmitted from the test pattern data transfer device 50 of the semiconductor test device to the PAD storage unit 2 as the first cycle, and then the data signal D1 is transmitted. Alternatively, the data signal D5 is continuously transmitted.
Then, as one next cycle, one address signal A2 is transmitted, and then the data signals D6 to D10 are continuously transmitted. The same applies to the third and subsequent cycles. These are sequentially stored in the PAD storage unit 2. When the PAD signal data is fetched and stored in the PAD storage unit 2, a STATUS signal indicating that the data is stored rises and is sent from the PAD storage unit 2 to the PAD storage unit read control unit 3.
The PAD storage unit read control unit 3 sends a READ signal to the PAD storage unit 2 based on the STATUS signal,
The address identification signal AE and the test pattern data PAD are read from the PAD storage unit 2. Here, when reading the test pattern data PAD and the address identification signal AE, the test pattern data PAD is read as ADA and the address identification signal AE is read as AE1. When AE1 is active, the address identification signal AE1 is taken into the address latch 7. At this time, the address latch 7 outputs A1 of the address signal ADRS, and the multiplexer 8
To the terminal 0 of. When the address identification signal AE1 is inactive, the address identification signal AE1 and the test pattern data ADA are input to the terminal 1 of the multiplexer 8. Here, the / AE1 signal is the address identification signal A
When E1 is inactive, this signal indicates a data cycle.
A signal obtained by ANDing one signal and the READ signal is defined as a selection signal DSA. The multiplexer 8 is selectively controlled by the selection signal DSA. Address identification signal AE
When 1 is active, the selection signal DSA is 0,
Select and control every other terminal 0 of the multiplexer 8 to
While the address signal ARS is output from the address signal ADRS as the DB signal, when the address identification signal AE1 is inactive, it indicates that this is a data cycle.
When the E1 signal is 1, the selection signal DSA is 1, and the terminal 1 of the multiplexer 8 is selectively controlled to output data signals D1 to D5 from the ADA signal as ADB signals. The address signal and the test pattern data read out as described above via the multiplexer 8 are:
Next, the pattern data is input to and stored in the pattern data storage unit 6 via the pattern data storage address control unit 4 and the test pattern data register 5. As described above, the conventional example is a PAD
The time relationship between the ADA signal and the ADA signal is as shown in FIG. 5, and there is a time gap between the ADA signal data, and this time gap is the time for transferring the ADA signal data. Of the transfer speed, and the transfer speed is degraded by the delay. According to the present invention, the PAD signal and the conventional AD
The time relationship between the ADB signal and the ADB signal corresponding to the A signal is as shown in FIG. 2, and the semiconductor test apparatus efficiently transfers test pattern generation data to the test pattern generator.

[Brief description of the drawings] FIG. 1 illustrates an embodiment. FIG. 2 is an operation time chart of the embodiment. FIG. 3 illustrates a semiconductor test apparatus. FIG. 4 is a diagram illustrating a conventional example. FIG. 5 is an operation time chart of a conventional example. [Explanation of symbols] 2 PAD storage 3 PAD storage unit read control unit 6 Pattern data storage 7 Address latch 8 Multiplexer 9 AND gate 20 Test pattern generator

Claims (1)

(57) [Claim 1] A timing generator, a test pattern generator, a waveform shaper, and a logical comparator are provided, and the test pattern generator is controlled according to a reference clock generated by the timing generator. The address, test pattern data, and control signal to be given to the test memory are output, and these data are respectively supplied to the waveform shapers and shaped into waveforms necessary for the test.
The memory under test M is controlled to write and read test pattern data by a control signal, the read data read from the memory under test is given to a logical comparator, and the expected value data and the read data output from the test pattern generator are And a test pattern data transfer device for transferring a test pattern data and an address identification signal for identifying whether the signal in the test pattern data is an address signal or a data signal to the test pattern generator. The test pattern generator has a PAD storage unit for storing test pattern data and an address identification signal and transmitting a STATUS signal in response to the test pattern data. The STATUS signal transmitted from the PAD storage unit Send READ signal to test pattern data storage An address identification signal and test pattern data are read in response to a READ signal from the PAD storage unit, and the address signal and the test pattern data are input and switched and output. A multiplexer having an address latch for taking in the address identification signal when the address identification signal is active and outputting the address signal to the multiplexer; and a signal indicating a data cycle when the address identification signal is inactive. AN between READ signal
An AND gate for outputting a signal taking D as a selection signal to a multiplexer, wherein the multiplexer outputs every other address signal when the selection signal is 0, and outputs a data signal when this is 1 according to the selection signal And a pattern data storage unit for storing a signal output from the multiplexer.