SU1322219A1 - Time check signal selector - Google Patents

Abstract

The invention can be used to periodically assign time scales and provides increased reliability by reducing the likelihood of skipping time check signals (SPB). The SPV selector contains triggers 1, 2, 3, detector 4, pulse generator (GI) 5, elements EXCLUSIVE OR b, 7, pulse counter (SI) 8, delay elements 9, 10. When the SPV arrives at the input of detector 4 on its output is formed by a video pulse. On the leading edge of the video pulse, the state of trigger 2 changes, and the trigger 1 is set to the state in which GU 5 begins to form a sequence of pulses simulating SPV. On the first impulse of the simulated SPV in SI 8 is entered 1, If the temporal mismatch of the leading edges of the signals from the flip-flops 2, 3 does not exceed the delay 9 specified by the element, then the output signal of the EXCLUSIVE OR element 7 is absent and in SI 8 is saved 1. After a certain time interval on The signal with SI 8 triggers 2, 3 are reset. For the next pulse GI 5 in SI 8, the second 1 is recorded. When recording in SI 8, the sixth 1, a signal is generated at its output that corresponds to the exact time on the time scale of the USSR SSGF. 1 il. (L with

Description

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The invention relates to spectroscale chronometry, in particular, to time signal selectors intended for periodic reference of the time scale.

The purpose of the invention is to build up reliability by reducing the likelihood of the time test signals to roar.

In the drawing, the pre-tailion structure is an electrical diagram of the general controller About the test check B1).

The time selector signal selector contains the first 1, second 2 and three traces 3 triggers, detector 4, generator

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5 pulses, the first is about and the second / elements are EXCLUSIVE US1EE EFI, counter 8 pulses and the first 9 and second 10 delay elements. I

The time selector selector works as follows.

The initial state, in which the selector is located in the absence of signals at its input, is always preceded by a preliminary mismatch in the following pulse input sequence and pulse sequence produced by the S 1gmpup generator at the inputs of the first element, DROPPUT OR 6, and, as a consequence, the initial state the error signal from the output of the second element is EXCLUSIVE OR 7 of the counter 8 pulses and the generator 5 pulses through the first trigger 1 .35

When a detector of the time check signal is input to the detector 4, a video pulse is formed at the detector output, with the leading edge of which the first trigger 1 is set to the state in which the pulse generator 5 begins to form a sequence of pulses that simulate a time test signal (rectangular pulse pulses with a 1s following period and the first pulse, coming from its output to the counting input of the pulse counter 8, are recorded in the memory of the pulse counter 8 1,

In this case, the second trigger 2 changes its state along the leading edge of the signal from the detector 4 output, and the trigger 3 from the generator 5 pulses .55

Temporary mismatch of the leading edges of signals from the outputs of the second 2 and third 3 triggers on the inputs

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the first element EXCLUSIVE OR 6 is taken into account by the constant time of the first delay element 9, and if this temporal mismatch does not indicate the set value of the first delay element 9, then the signal from its output to the input of the second element EXCLUSIVE OR 7 is absent, and since there is also no signal at the other input (output signal of the pulse counter 8, generated at the other input through the second delay element 10), the output signal of the second element is EXCLUSIVE; OR 7 is absent, and in the counter 8 pulses, recorded 1 is stored until the next signals are received at the inputs of the first element EXCLUSIVE OR 6.

The second 2 and third 3 triggers are returned to the initial state by a signal from the first output of the counter 8 pulses at a time interval equal to B1 of the pulse duration received at its counting input from the generator 5 of pulses.

After a time interval, the pulse generator 5 forms a next pulse at its output, the leading edge of which the second 1 is recorded in the pulse counter 8, and the third trigger 3 changes its state again, the leading edge of the signal and, if at this time a signal arrives from the output of the detector 4 to the input of the second trigger 2, then the result of the comparison of the signals from the outputs of the second 2 and third 3 triggers at the inputs of the first element EXCLUSIVE OR 6 also has no output signal at the output The second element is DEPOSITING OR 7, i.e. Recorded second 1 is stored in the memory of the counter 8 pulses. When the sixth pulse arrives at the selector input, a time check signal from the generator output 5 pulses the next (sixth) pulse into the counter 8 pulses, a pole 1 is recorded and at its second output output signal of the selector and corresponding to the exact time on the time scale of the GSVCH USSR.

The duration of the output signal is determined by the time constant of the second delay element 10.

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through which the output signal acts on one of the inputs of the second element EXCLUSIVE OR 7 and, since there is no signal on the other input, then a Set O signal is generated at the output, setting the pulse counter 8 and the pulse generator 5 to its initial state ( standby mode).

Claims (1)

Invention Formula A time check signal selector containing the first delay element, a pulse counter and a serially connected detector and a first trigger whose output is connected to the input. Setting the pulse generator to zero, in order to increase reliability by decreasing the probability of skipping the time test signals, the second trig-t ep, the first input of which is connected to g O 50 194 detector output, and the first element EXCLUSIVE OR, the output of which is Source to the input of the first delay element, as well as the third trigger, the output of which is connected to the second input of the first element EXCLUSIVE OR, and the series-connected second delay element and the second element EXCLUSIVE OR, the output of which connected to the installation input of the pulse counter and the second input of the first trigger, while the output of the pulse generator is connected to the counting input of the pulse counter and the first input of the third trigger, the second input of which oedinen the first output of the pulse counter and a second input of the second flip-flop, the output of the first delay element connected to a second input of the second exclusive OR element, a second pulse counter output is connected to an input of the second delay element and is output devices.