JPS5755433A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS5755433A
JPS5755433A JP55129501A JP12950180A JPS5755433A JP S5755433 A JPS5755433 A JP S5755433A JP 55129501 A JP55129501 A JP 55129501A JP 12950180 A JP12950180 A JP 12950180A JP S5755433 A JPS5755433 A JP S5755433A
Authority
JP
Japan
Prior art keywords
output
taken
input
signal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55129501A
Other languages
Japanese (ja)
Other versions
JPS6160456B2 (en
Inventor
Hiroyuki Yanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55129501A priority Critical patent/JPS5755433A/en
Publication of JPS5755433A publication Critical patent/JPS5755433A/en
Publication of JPS6160456B2 publication Critical patent/JPS6160456B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom

Abstract

PURPOSE:To achieve a synchronizing circuit between multi-chips effective to an LSI, by making common the original oscillation at the time of a synchronism of a system clock and connecting input and output pins of each chip. CONSTITUTION:A signal obtained by inputting an original oscillation signal FOS to an inverter INV12 is taken as a write-in signal for shift registers SR1-3, and the original oscillating signal is taken as a readout signal. The output of the SR1 is taken as the input to a NAND gate 6 and an INV4, and the output of the INV4 is taken as the 1st system clock. The output of the SR2 is taken as the input to the SR3 and the gate 6, the output of the SR3 is taken as the input to the gate 6 and the INV5, and the output of the INV5 is taken as the 2nd system clock. The output of an INV7 is connected to an input and output terminal IO via an output buffer 8 and it is taken as the input to an INV9. The output of the INV9 is taken as the input to an SR11 via an INV10 and a gate 11.
JP55129501A 1980-09-18 1980-09-18 Synchronizing circuit Granted JPS5755433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55129501A JPS5755433A (en) 1980-09-18 1980-09-18 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55129501A JPS5755433A (en) 1980-09-18 1980-09-18 Synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS5755433A true JPS5755433A (en) 1982-04-02
JPS6160456B2 JPS6160456B2 (en) 1986-12-20

Family

ID=15011037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55129501A Granted JPS5755433A (en) 1980-09-18 1980-09-18 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS5755433A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01195640A (en) * 1988-01-29 1989-08-07 Matsushita Electric Ind Co Ltd Image display device
JPH01195642A (en) * 1988-01-29 1989-08-07 Matsushita Electric Ind Co Ltd Image display device

Also Published As

Publication number Publication date
JPS6160456B2 (en) 1986-12-20

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