JPS5768954A - Memory controller - Google Patents

Memory controller

Info

Publication number
JPS5768954A
JPS5768954A JP55145300A JP14530080A JPS5768954A JP S5768954 A JPS5768954 A JP S5768954A JP 55145300 A JP55145300 A JP 55145300A JP 14530080 A JP14530080 A JP 14530080A JP S5768954 A JPS5768954 A JP S5768954A
Authority
JP
Japan
Prior art keywords
counter
write
read
rom7
signal generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55145300A
Other languages
Japanese (ja)
Other versions
JPH0262982B2 (en
Inventor
Seiichi Yokozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP55145300A priority Critical patent/JPS5768954A/en
Publication of JPS5768954A publication Critical patent/JPS5768954A/en
Publication of JPH0262982B2 publication Critical patent/JPH0262982B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To stably operate without avoiding the super-position of asynchronous write/read operation, by using a time required for parallel convertion of digital data transmitted for each bit serially. CONSTITUTION:By using a counter 20 calculating transmission clock for data serial-parallel conversion and periodic read/write instruction signal generating circuit obtained from the frequency division of a reference clock produced at another reference clock signal generating circuit 5, timing signals f, g, j are produced from a timing generation circuit such as an ROM7 programmed in advance by taking the counter outputs X0-X3 of the counter 20 and an instruction signal output h' as the address input, and the program written in the ROM7 is suitably selected, the operation having higher frequency is given priority among write/read operations so that the mutual operations are not overlapped, allowing to avoid malfunction due to delay of elements.
JP55145300A 1980-10-17 1980-10-17 Memory controller Granted JPS5768954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55145300A JPS5768954A (en) 1980-10-17 1980-10-17 Memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55145300A JPS5768954A (en) 1980-10-17 1980-10-17 Memory controller

Publications (2)

Publication Number Publication Date
JPS5768954A true JPS5768954A (en) 1982-04-27
JPH0262982B2 JPH0262982B2 (en) 1990-12-27

Family

ID=15381950

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55145300A Granted JPS5768954A (en) 1980-10-17 1980-10-17 Memory controller

Country Status (1)

Country Link
JP (1) JPS5768954A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228441A (en) * 1983-06-10 1984-12-21 Nec Home Electronics Ltd Clock forming circuit of pcm recording and reproducing device
JPH01162925A (en) * 1987-12-18 1989-06-27 Fujitsu Ltd Asynchronous speed converting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228441A (en) * 1983-06-10 1984-12-21 Nec Home Electronics Ltd Clock forming circuit of pcm recording and reproducing device
JPH01162925A (en) * 1987-12-18 1989-06-27 Fujitsu Ltd Asynchronous speed converting circuit

Also Published As

Publication number Publication date
JPH0262982B2 (en) 1990-12-27

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