KR100280426B1 - Apparatus of frequency conversion - Google Patents

Abstract

The present invention relates to a frequency converter. In the conventional apparatus, since a first-in first-out method is used, a large number of gates are required and not only a large area is required in chip design, but also a circuit for read / write control of the first-in first-out memory is complicated. There was a problem. Accordingly, the present invention includes a linear filter for receiving and filtering a linear signal at a clock a cycle; A counter unit for outputting a selection signal at a clock cycle; By configuring the signal output from the linear filter as a selection output unit for outputting a value selected by the selection signal of the counter unit, not only the first-in-first-out memory is used, but also the circuit is simplified and the control circuit can be simplified to reduce the chip size. To reduce latency.

Description

Frequency converter {APPARATUS OF FREQUENCY CONVERSION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter, and more particularly, to a frequency converter that minimizes delay time without using a first-in, first-out memory in transmitting data from devices having different operating frequencies.

1 is a configuration diagram of a conventional frequency converter, and a linear filter 1 for receiving and filtering a linear signal IN, as shown therein; An enable signal generator 2 for generating an enable signal en; A write address generator (3) which receives the enable signal (en) from the enable signal generator (2) and is enabled and outputs a write address (wa); A read address generator 4 for generating a read address ra; The signal IN filtered and output from the linear filter 1 is received and stored in the address by the write address wa output from the write address generator 3, and the read address generator 4 A first-in-first-out memory 5 for outputting data of the address by the read address ra output from the above is described.

The signal IN passing through the linear filter 1 is input to the first-in, first-out memory 5, and is written by the write address generator 3 by the enable signal en generated by the enable signal generator 2. It is stored in the first-in, first-out memory 5 by the output write address wa. At this time, the linear filter 1, the write address generator 3, and the enable signal generator 2 operate in a cycle of clock a (cka), and the dummy (a, beta) of the coefficients α and β of the linear filter 1 The dummy value is for correcting the period difference between the different clocks cka and ckb and thus is not stored in the first-in, first-out memory 5.

The read address generator 4 outputs the read address ra to the first-in first-out memory 5 at a clock ratio ckb having a different period, and outputs the data at the read address ra to the clock ratio ckb. The output will be made at the interval of.

Therefore, the value stored in the first-in, first-out memory 5 in the period of the clock cka is output by the clock ratio ckb of another period.

FIG. 2 is a coefficient table of the linear filter 1 of FIG. 1, wherein a dummy value is not written to the first-in, first-out memory 5 according to the enable signal en of the enable signal generator 2. .

However, in the conventional apparatus, since the first-in first-out method is used, a large number of gates are required, and a large area is required when designing a chip, and a circuit for read and write control of the first-in first-out memory is complicated.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and the frequency converter device not only simplifies the circuit by using the first-in, first-out memory but also makes the control circuit simple and reduces the chip size. The purpose is to provide.

1 is a block diagram of a conventional frequency converter.

FIG. 2 is a coefficient table of the linear filter of FIG.

3 is a configuration diagram of the frequency converter of the present invention.

4 is a configuration diagram of the selective output unit in FIG. 3;

5 is a timing diagram of each part of FIG. 4;

* Description of the symbols for the main parts of the drawings *

10: linear filter 20: counter part

30: Selective output unit D1 to D5: Reservoir

MUX: Multiplexer

According to an aspect of the present invention, there is provided a frequency converter including: a linear filter configured to receive and filter a linear signal at a clock a cycle; A counter unit for outputting a selection signal at a cycle of the clock-clock; It is achieved by configuring the signal output from the linear filter as a selection output section for outputting a value selected by the selection signal of the counter section.

The selection output unit may include: a first storage unit configured to store an output signal of the linear filter at a period of the clock-clock; Second and fourth storage units configured to sequentially store the output of the first storage device at a falling edge of a clock ratio; Third and fifth reservoirs configured to sequentially store the output of the first reservoir at the rising edge of the clock ratio; With reference to the accompanying drawings, an embodiment according to the present invention is composed of a multiplexer which receives the output signals of the fourth and fifth reservoirs and selectively outputs them by the selection signal of the counter. As follows.

3 is a configuration diagram of the frequency converter of the present invention, and a linear filter 10 for receiving and filtering a linear signal IN at a cycle of clock a as shown in FIG. A counter unit 20 for outputting a selection signal sel at a cycle of the clock acar; The signal output from the linear filter 10 includes a selection output unit 30 for outputting a value selected by the selection signal sel of the counter unit 20.

FIG. 4 is a detailed configuration diagram of the selection output unit 30 shown in FIG. 3. As shown in FIG. 3, the first storage unit stores the output signal Oflt of the linear filter 10 at a cycle of clock acka. (D1); Second and fourth reservoirs D2 and D4 which sequentially store the output signal X0 of the first reservoir D1 at the falling edge of the clock ratio ckb; Third and fifth reservoirs D3 and D5 which sequentially store the output signal X0 of the first reservoir D1 at the rising edge of the clock ratio ckb; The multiplexer MUX receives the output signals X11 and X21 of the fourth and fifth reservoirs D4 and D5 and selectively outputs them by the selection signal sel of the counter 20. The operation and operation of the present invention configured as described above will be described.

FIG. 5 is a timing diagram of each part of FIG. 4, where the difference between the two clocks cka and ckb is 1, and 'X' is not used among the values of X1, X11, X2, and X21, and this value is a multiplexer (MUX). Is discarded by the selection signal sel.

The linear signal IN outputs the filtered signal Oflt through the linear filter 10. The output signal Oflt includes a dummy value and is used as an input value of the selective output unit 30 in the conventional manner. The output signal X0 is generated via the first reservoir D1, and the output signal X0 generates X1 at the falling edge of the clock ratio ckb and X2 at the rising edge. The output signals X1 and X2 generate X11 and X21 through the fourth and fifth storage units D4 and D5, respectively, and the two output signals X11 and X21 are input to the multiplexer MUX. It is selected and output by the selection signal sel outputted at 20. At this time, the ratio of the clock acre cka to the clock ratio ckb is M / N, and M and N are the number of samples between the same rising edges of the clock acre cka and the clock ratio ckb.

As described above, the frequency converter of the present invention not only simplifies the circuit by using the first-in, first-out memory but also simplifies the control circuit, thereby reducing the chip size and reducing the delay time.

Claims (1)

A linear filter configured to receive and filter the linear signal at a clock a cycle; A counter unit for outputting a selection signal at a cycle of the clock-clock; A first storage unit for storing the output signal of the linear filter at a period of the clock-clock; Second and fourth storage units configured to sequentially store the output signal of the first storage device at a falling edge of a clock ratio; Third and fifth storage units configured to sequentially store output signals of the first storage device at rising edges of the clock ratio; And a multiplexer configured to receive the output signals of the fourth and fifth reservoirs and selectively output the selected signals by the selection signal of the counter unit.

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