JPH11186996A - Phase transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a memory of a large capacity, such as a FIFO memory by receiving a digitized delay D so as to delay received data and to obtain in-device data. SOLUTION: A synchronization circuit 5 gives the position of a reference signal in each frame of input data 1 to a data hold section as input data position P. A delay in an in-device timing signal 7 with respect to the input data 1 is obtained, based on the input data position P and the in-device timing signal 7. The delay D is fed to a variable delay circuit 3. The variable delay circuit 3 delays the input data 1 by this delay D and provides an output of the delayed data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change circuit suitable for receiving relatively short-period digital data, shifting the phase of the digital data, and transferring the digital data to an output side.

[0002]

2. Description of the Related Art For example, ST in a digital communication network
At the end of the frame transmission path, when digital data having one frame consisting of 8 bits is input serially, the phase of this data is shifted and sent to the output side. A circuit that performs such processing is called a phase change circuit, and is configured using a FIFO (first-in first-out) memory that accumulates input data as needed for the phase shift and outputs the accumulated data.

This circuit detects a synchronization pattern in input data before storing the input data in a FIFO memory. The position where the synchronization pattern is detected is the head position of one frame. This is set as the input timing, and the input data is sequentially stored in the FIFO memory frame by frame. Then, on the output side, the data is taken out from the FIFO memory in the order of input using the timing signal on the output side. Even if the phase of the input-side timing signal and the phase of the output-side timing signal are out of phase with each other, the phase can be adjusted on the output side by this processing. In this way, the phase change processing of the input data and the output data has been performed.

[0004]

However, the above-mentioned prior art has the following problems to be solved.
In a configuration in which input serial data is stored in a FIFO memory by a predetermined amount and output data is extracted therefrom at a predetermined timing, the memory capacity tends to be large. Therefore, there is a problem that the hardware configuration becomes excessive in data transmission processing of ST frames, bearer signals, and the like having a relatively short cycle.

Further, when a frame to be phase-shifted is multiplexed in an input signal, it is necessary to combine a number of phase-shifting circuits having the same function. This has a problem that the circuit configuration becomes very complicated and wasteful.

[0006]

The present invention employs the following structure to solve the above problems. <Structure 1> A delay amount calculation unit that calculates a delay amount of the input data with respect to an in-device timing signal of a device that receives input data, and a delay amount that receives the input data and is output by the delay amount calculation unit. And a variable delay circuit for delaying input data by a predetermined time and outputting the delayed data.

<Structure 2> In structure 1, the delay amount calculating section detects the position of the reference signal in each frame constituting the input data, and outputs this as the input data position; And a data hold circuit that receives and holds the input data position output from the device and outputs the input data position to the variable delay circuit as a delay amount for each frame at the timing of input of the internal timing signal. Phase transfer circuit.

<Structure 3> A delay amount calculation unit for calculating a delay amount of the input timing signal of the input data for each frame with respect to a timing signal in the device of the device receiving the input data, and a delay amount calculating unit for receiving the input data for each frame. ,
A variable delay circuit that delays input data for each frame by a time corresponding to the delay amount output from the delay amount calculation unit and outputs the delayed data.

<Structure 4> In Structure 3, the delay amount calculating section holds a synchronous circuit including a counter which starts counting in response to an input timing signal of input data, and holds a count value output from the synchronous circuit by a timing signal in the device. And a data hold circuit for obtaining a delay amount.

<Structure 5> In the structure 3, in the delay amount calculating section, a first-in first-out memory for sequentially storing the input data position of each frame of the input data and outputting the stored data in the order in which the data is stored,
A data hold circuit for obtaining an amount of delay by holding an output of the first-in-first-out memory by a timing signal in the apparatus; and a variable delay circuit having a first-in-first-out memory for receiving input data and arranging them in the order of output. Phase transfer circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below using specific examples. <Example 1> FIG. 1 is a block diagram showing an example of a phase change circuit according to the present invention. The circuit shown in this figure is
1 shows a principle configuration of the present invention. The input data 1 is delayed in the variable delay circuit 3 by a time corresponding to a predetermined delay amount and output as in-device data 2. The variable delay circuit 3 includes a phase change processing unit 4.
Further, there is provided a synchronization circuit 5 which receives the input data 1, detects the specific signal position, and outputs a signal corresponding to the signal position as the input data position P. Further, the output of the synchronization circuit 5 is temporarily held by the data hold unit 6. This is taken out by the input of a timing signal in the apparatus, and is output to the phase change processing unit 4 as the delay amount D.

The data hold unit 6 stores in-device data 2
Timing signal 7 for controlling the transfer of each frame
Enter. The synchronizing circuit 5, the phase change processing unit 4, and the data hold unit 6 are all configured to receive an internal clock 8 for controlling operation timing in the device.

Conventionally, a variable delay circuit 3 has a FIFO
Was used. This FIFO arranges and holds serially input data one frame at a time, and extracts each frame to the output side at a timing shifted by a time corresponding to a phase shift. To achieve this, the FIFO
It is necessary to prepare a memory having a sufficient storage capacity in consideration of the maximum phase shift time. For example, one frame is 8
Since there is a phase shift of up to 8 bits for bits,
A FIFO memory having a capacity capable of storing at least eight frames is required.

On the other hand, in the present invention, since the variable delay circuit 3 is used, for example, the simplest circuit only requires a buffer of about 8 bits on each of the input side and the output side. In this way, the storage capacity is made sufficiently small, and a general-purpose integrated circuit can be used as a component.

FIG. 2 is a block diagram showing a specific example of the phase transfer circuit according to the first embodiment. The variable delay circuit 3 shown includes a holding circuit 11 and a selection output circuit 12. A general-purpose IC (integrated circuit) as shown in the figure is used for each of the two circuits.

The synchronizing circuit 5 shown in the figure has a counter (not shown) which starts counting when the first bit of the input frame is input, and starts counting from the beginning when counting up to the last bit of the input frame. This count value is output as the input data position P. If the frame length is 8 bits, the input data position P can be represented by 3-bit digital data. This is input to the data hold unit 6. The data hold unit 6 can also be constituted by a simple flip-flop as shown in the figure. And
The input data position P is held in this flip-flop,
This signal is output to the selection output circuit 12 at the timing when the in-device timing signal 7 is input.

FIG. 3 shows an operation timing chart of the circuit of the first embodiment. The operation of the circuit of the specific example 1 as shown in FIG. 2 will be described with reference to FIG. First, FIG.
Input data as shown in FIG. 2 is input to the variable delay circuit 3 and the synchronization circuit 5 shown in FIG. The input data 1 input to the variable delay circuit 3 is serially input to and held in the holding circuit 11 by, for example, 8 bits. When 8-bit data is input, the data is transferred to the selection output circuit 12 side in parallel. The selection output circuit 12 performs an operation of shifting the 8-bit signal by a bit corresponding to the delay amount output from the data hold unit 6 and reading it as the in-device data 2.

The input of the input data 1 causes the synchronization circuit 5
Generates an input timing signal as shown in FIG. Further, a counter (not shown) incorporated in the synchronizing circuit 5 is reset to “0” at the rise of the input timing signal, and thereafter, at the timing of the output clock shown in FIG. Count up. This count value returns to “0” again when counting up to “7”. As a result, data corresponding to the input data position P indicating which bit from the start position of the frame is currently serially input is output from the synchronization circuit 5 and input to the data hold unit 6.

On the other hand, from the output side, the in-device timing signal 7 on the output side is input to the data hold unit 6. When the output timing signal is input to the data hold unit 6 at the timing shown in FIG. 3D, the input data position P becomes "5".
At the time, the internal timing signal 7 is input.
The numerical value “5” is held in the data hold unit 6.
This data becomes the amount of delay of the output data with respect to the input data, and thereby the selection output circuit 12 is controlled. That is, the data held in the selection output circuit 12 is sequentially read from a position shifted by the number of bits corresponding to the delay amount. As a result, as shown in FIG.
Output data obtained by delaying input data by a predetermined amount is taken out as in-apparatus data 2.

<Effect of Specific Example 1> Input data is received and held in the variable delay circuit 2, a delay of the input data with respect to a timing signal in the device is detected, and the input data is delayed by an amount corresponding to the delay. Since the configuration is such that the data is extracted with a delay, a circuit for holding a large amount of input data is not required, and a small-scale and simple phase transfer circuit is realized.
Further, since the circuit scale is small, power consumption can be reduced. The synchronization circuit 5 for obtaining the delay amount as described above
The data hold unit 6 and the data hold unit 6 will be referred to as a delay amount calculation unit, but the method of calculating the delay amount is not limited to the above example.

<Embodiment 2> In the following example, the circuit operation of the embodiment 1 shown in FIG. 2 is used as a basic principle, and a circuit is provided so that a similar phase change process can be performed on a signal multiplexed for each frame. Configured. FIG. 4 is a block diagram of a phase change circuit according to the second embodiment. This device is provided with a data FIFO 14 having a function of rearranging the data while serially receiving the input data 1 in the variable delay circuit 3 and holding only the multiplexed data. The configuration of the selection output circuit 12 on the output side is described in Example 1.
It is similar to that of Further, on the output side of the synchronizing circuit 16 receiving the input data 1, a position FIFO 17 for holding the same number of multiplexed data as the input data position D similar to that described in the first embodiment is provided.

Since the configuration of the synchronization circuit 16 is slightly different from that of the first embodiment, another reference numeral is given. The part of the circuit that receives the input data 1 and supplies the delay amount D to the variable delay circuit 3 at the timing when the in-device timing signal 7 is input is the same as that of the first embodiment.

FIG. 5 shows an operation timing chart of the circuit of the second embodiment. FIG. 5A shows an internal clock, and FIG.
(B) is input data. As shown in the figure, input data is serially input for 20 bits from left to right on the top row of the figure, and then, for the data shown in FIG. FIFO14
Is written and stored.

In the case of the specific example 1 shown in FIG. 3, one frame is composed of signals numbered 0 to 7 that are input serially 8 bits at a time. On the other hand, in the example of this figure, when the input data shown in FIG. 5B is viewed in the vertical direction, 8 bits each constitute one frame. The bit indicated by (F) in each frame is used as a reference signal. Therefore,
The position of the reference signal for each frame is the input data position P. This data is output from the synchronization circuit 16. For example, in the case of the example shown in FIG.
Looking at the column, the reference signal is at the first bit. Therefore, the output of the synchronization circuit 16 becomes "1". Focusing on the second 8-bit column from the left, the position of the reference signal is the second bit. Therefore, the synchronization circuit 16 outputs a numerical value “2”.

In the example of FIG. 5B, data corresponding to the position of the reference signal such as 1, 2, 4, 7, 6, 5 is input from the synchronization circuit 16 to the position FIFO 17. And is retained. On the other hand, the data FIFO 14 has 8
Holds data of bit × 20. Also, FIF for position
O17 holds 3 bits × 20 data. The input data positions P held in the position FIFO 17 are sequentially supplied to the data hold unit 6. When the in-device timing signal 7 is input to the data hold unit 6, this is the delay amount D
Is supplied to the variable delay circuit 3. The operation of the selection output circuit of the variable delay circuit 3 is the same as that of the first embodiment.

In the data FIFO 14, the input data shown in (b) of FIG. 5 is arranged from left to right in the order of the first line from the first line to the second line and the third line. Enter serially in the direction you are going. These are FIFOs for data
When the data is input to the memory 14, the data is arranged in order one line at a time, and a data array having the contents shown in FIG. 5B is finally obtained. Thereafter, the selection output circuit 12 outputs 8 bits each of the input data shown in FIG. 2
If the bits of each frame of the 0-frame input data are counted in the same manner as in the first embodiment, the synchronization circuit 16
For example, a configuration in which 20 counters are provided to individually obtain the input data position P may be adopted.

However, this causes the circuit scale to be too large. Therefore, as shown in FIG.
When the position of the reference signal is detected from the input data to be serially input to the position FIFO 6, the position of the reference signal is detected in order in each case.
7 is stored. Therefore, in this specific example, the positions of all the reference signals are written to the position FIFO 17 by returning the output of the position FIFO 17 to the synchronization circuit 16 eight times for eight rows. This, then,
The first vertical column 8 shown in FIG.
The input position P of each data is output to the data hold unit 6 in order from the input data position P of the bit data.

In the manner described above, the data of each frame of the multiplexed input data as shown in FIG.
In either case, the phase change processing is performed so that the position of the reference signal (F) is at the head, and the data becomes in-apparatus data as shown in FIG. Position FIFO 17 and Data FIFO 1
4 is all cleared at the input timing of the multi-period pulse shown in FIG. 5D and returns to the initial state.

<Effect of Specific Example 2> As described above, the input data multiplexed for each frame is subjected to the phase change based on the input data position P in the same manner as in the specific example 1, and Data can be obtained. Further, since such a function is realized by a variable delay circuit, a synchronous circuit, a data hold unit, and the like having a minimum storage capacity, the circuit can be downsized. Thus, it can be effectively used at the end of a transmission path having an ST frame in a general transmission device.

<Embodiment 3> FIG. 6 is a block diagram of a phase transfer circuit according to Embodiment 3. Here, the circuit of the specific example 2 is replaced with a plurality of X50s in a more general transmission device.
The configuration is such that it can be used for multi-frame phase alignment. In the data FIFO 14 shown in the figure, the bit width is set by the number of bits of the frame to be subjected to the phase matching of the input data. In the case of the specific example 2, this bit width is 8, but in the specific example 3, it is, for example, 20 bits.

The selection output circuit 15 has a configuration having a data receiving terminal corresponding to the bit width, and its function itself is not different from those shown in the first and second embodiments. The configurations of the synchronization circuit 16, the position FIFO 17, the data hold unit 6, and the like are the same as those of the second embodiment.

FIG. 7 shows an operation timing chart of the circuit of the third embodiment. FIG. 7A shows an internal clock. Also in this circuit, as shown in FIG. 7B, the input data is sequentially input from left to right from the top row to each row. That is, as shown in FIG. 7 (b), one line of data at the uppermost portion from the left to the right of the drawing is received, and data of one line of the next line is received in order.
The input from the upper left 8-bit data to the lower right 8-bit data shown in FIG. The point is the same as that of the specific example 2. However, the data is 8 bits per unit when viewed serially. In this cycle, a multi-period pulse shown in FIG. 7D is output.

As shown in FIG. 7 (b), the signals received in this manner are F bits, 8 bits each, when viewed in the vertical direction.
1, F2, F3,..., F20.
In this example, 8 bits × 20 are treated as one frame. Therefore, the phase transfer is performed using 8 bits as one unit. Assuming that the data array of the leftmost frame of the input data is normal, the data array of the center frame has F1 at the fourth position from the bottom (hidden in the figure). Therefore, the data position P is set to the 16th from the top, and the same phase change as in the specific example 2 is performed.

As described above, a data structure in which 8 bits are defined as one unit and are arranged in an arbitrary number as viewed in the vertical direction of the drawing is a relatively common one for a low-speed transmission device, that is, a low-speed terminal interface. is there. Therefore, the present invention can be widely used for such a low-speed device.

<Effect of Specific Example 3> Not only data multiplexed in 1-bit units but also data multiplexed in 8-bit units, for example, are multiplexed on the basis of the delay amount using a relatively small-capacity FIFO. Output data can be obtained at a predetermined timing for each combination of the converted data.
As a result, there is an effect that the multiplexing process can be performed with a relatively simple configuration while the memory capacity can be reduced and downsized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a phase transfer circuit according to the present invention.

FIG. 2 is a block diagram of a phase change circuit according to a specific example 1;

FIG. 3 is an operation timing chart of the circuit of the specific example 1.

FIG. 4 is a block diagram of a phase change circuit according to a specific example 2;

FIG. 5 is an operation timing chart of the circuit of the specific example 2.

FIG. 6 is a block diagram of a phase change circuit according to Example 3;

FIG. 7 is an operation timing chart of the circuit of the specific example 3.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input data 2 In-device data 3 Variable delay circuit 5 Synchronous circuit 6 Data hold part 7 In-device timing signal

Claims (5)

[Claims] 1. A delay amount calculation unit for calculating a delay amount of the input data with respect to an internal timing signal of a device for receiving input data, and a delay amount output from the delay amount calculation unit after receiving the input data. A variable delay circuit for delaying input data by a corresponding time and outputting the delayed data. 2. The synchronization circuit according to claim 1, wherein the delay amount calculating section detects a position of the reference signal in each frame constituting the input data, and outputs the detected position as an input data position. And a data hold circuit for receiving and holding an input data position to be output, and outputting the input data position as a delay amount for each frame to a variable delay circuit at a timing of input of a timing signal in the apparatus. Phase transfer circuit. 3. A delay amount calculating unit for calculating, for each frame, a delay amount of the input timing signal of the input data with respect to a timing signal in the device of the device for receiving the input data, and receiving the input data for each frame, A variable delay circuit that delays input data for each frame by a time corresponding to a delay amount output from the delay amount calculation unit and outputs the delayed data. 4. The delay amount calculating section according to claim 3, wherein the delay amount calculating section holds a synchronous circuit including a counter which starts counting in response to an input timing signal of input data, and holds a count value output from the synchronous circuit by a timing signal in the device. And a data hold circuit for obtaining a delay amount by using a phase change circuit. 5. The first-in-first-out memory according to claim 3, wherein the delay amount calculating section sequentially stores the input data positions of the input data for each frame, and outputs the stored data in the order in which they are stored. And a data hold circuit for obtaining a delay amount by holding the input data, and the variable delay circuit includes a first-in first-out memory for receiving input data and arranging the data in an output order.