JPH06332668A - Synchronization circuit - Google Patents

Abstract

PURPOSE:To provide a synchronization circuit capable of coping with variable length data. CONSTITUTION:This circuit is provided with first and second shift circuits 6 and 7 where data is transferred by synchronizing with a shift pulse and the number of times of shift is variable from the input of the data to the output of data, a data length setting circuit 11 setting the number of times of shift in these shift circuits 6 and 7, a multiplexer 5 alternately supplying data from a encoder/decodec circuit 2 to the shift circuits 6 and 7, a multiplexer 8 alternately selecting the data from the shift circuits 6 and 7 by the phase which is reverse to that of the multiplexer 5 and outputting it to a memory circuit 3 and a shift pulse generation circuit 10 generating the shift pulse which synchronizes with the timing of the device on an input side at the time of writing the data of the shift circuits 6 and 7 and generating the shift pulse which synchronizes with the timing of the device on an output side at the time of reading the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit used in an image data processing device for encoding and storing image data.

[0002]

2. Description of the Related Art For example, when storing image data in a memory circuit, the image data is encoded in order to reduce the amount of data. For example, an image is divided into several blocks, each block is coded and stored in a memory. Further, when reproducing the image data, the encoded data stored in the memory is read and decoded.

Since the operation timing of the encoding / decoding process and the write / read operation of the memory are generally different from each other, some kind of synchronizing means is required.

As described above, in order to synchronize circuits having different timings before and after the signal path, the FIFO (f
An irst-in first-out buffer, a ping-pong buffer, or the like is used.

[0005]

When encoding image data, the length of the encoded data changes depending on the size of the block size, the quality of the target image, the processing speed, and the like. For example, the larger the block size, the longer the data length.

However, the above FIFO buffer,
In the conventional synchronizing circuit using a ping-pong buffer or the like, the data length that can be handled is limited to a fixed data length, and there is a problem that variable-length data cannot be handled.

Therefore, an object of the present invention is to provide a synchronizing circuit capable of handling variable length data.

[0008]

In order to achieve the above-mentioned object, the present invention is provided between an input side device and an output side device which are asynchronous with each other, and has a variable length from the input side device to the output side device. A synchronous circuit for transferring data, wherein the data is transferred in synchronization with a shift pulse, and the number of shifts from the input to the output of the data is variable, and the two shift circuits. Means for setting the number of shifts in the circuit, first selecting means for alternately supplying data from the input side device to the two shift circuits, and first selection of data from the two shift circuits. Second selecting means for alternately selecting and outputting to the output side device in a phase opposite to that of the means, and a shift in synchronization with the timing of the input side device when writing data in the two shift circuits. Generating a pulse, said when reading data of the shift circuit, characterized in that it comprises a shift pulse generating means for generating a shift pulse coincident with the timing of the output-side device.

[0009]

The data from the input side device is alternately supplied to and written in the two shift circuits by the first selecting means. When writing data to the shift circuit, a shift pulse synchronized with the timing of the input side device is supplied to the shift circuit, and the data is written in synchronization with the timing of the input side device. Data is read from the other shift circuit in parallel with the data writing to the one shift circuit.
This data reading is performed in synchronization with the timing of the output side device. When the data is read from the shift circuit, the reading is started from a predetermined position corresponding to the data length. As a result, it becomes possible to transfer data between the input side device and the output side device which are asynchronous with each other regardless of the data length.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention will be specifically described below based on embodiments with reference to the drawings.

FIG. 1 is a block diagram of a data processing device to which the synchronizing circuit of the present invention is applied.

In the figure, reference numeral 1 is a data input / output circuit for transmitting / receiving data of n-bit representation to the outside. Reference numeral 2 denotes an encoding / decoding circuit that block-codes the data from the data input / output circuit 1 and transfers it to the synchronizing circuit 4 when data is input, and decodes the data from the synchronizing circuit 4 and outputs it to the data input / output circuit 1 when outputting data. It is assumed that the encoding / decoding circuit 2 has a variable encoding rate and there are a plurality of types of output data length. Here, the block coding is x × y × by compressing data for each pixel block composed of x pixels × y pixels with respect to data in which one pixel is expressed by m bits.
This refers to the process of making the data amount less than m bits. Reference numeral 3 denotes a memory circuit for storing the data from the synchronizing circuit 4. Reference numeral 4 denotes a synchronizing circuit for matching the operation timings of the encoding / decoding circuit 2 and the memory circuit 3. The synchronization circuit 4 transfers data in units of blocks between the encoding / decoding circuit 2 and the memory 3.

FIG. 2 shows a detailed block diagram of the synchronizing circuit 4 shown in FIG. In the figure, numeral 5 indicates a multiplexer (indicated by MUX in the figure) for selecting an input to the synchronizing circuit 4. The multiplexer 5 can select the data input direction for the encoding / decoding circuit 2 and the memory circuit 3. Reference numerals 6 and 7 denote first and second shift circuits capable of changing the number of shifts from the input to the output in order to adjust the data input / output timing. As will be described later, the first and second shift circuits 6 and 7 are configured to output the input data when the input data is shifted a plurality of times. Reference numeral 8 denotes a multiplexer that selects the output from the first shift circuit 6 or the second shift circuit 7 and outputs it to the encoding / decoding circuit 2 or the memory circuit 3. Reference numeral 9 denotes a multiplexer for selecting an output destination from the synchronizing circuit 4. By this multiplexer 9, the data output direction can be selected for the encoding / decoding circuit 2 and the memory circuit 3. Reference numeral 10 denotes a shift pulse generation circuit for supplying the first and second shift circuits 6 and 7 with a shift pulse synchronized with the operation timing of the encoding / decoding circuit 2 or the memory circuit 3. Reference numeral 11 is a data length setting circuit that sets the number of shifts from the input of data to the output of the multiplexer 8.

FIG. 3 is a block diagram showing the configuration of the first shift circuit 6 and the multiplexer 5 shown in FIG. 2 in more detail. The first shift circuit 6 is composed of a plurality of registers 6a, 6b, 6c, ... Connected in series.
The data in each register is shifted byte by byte in synchronization with the shift pulse SP supplied from the shift pulse generation circuit 10.

On the other hand, the multiplexer 8 is provided with a selection circuit 8a for selecting an output from each register 6a, 6b, 6c, ... Of the first shift circuit 6 and an input / output to which an output from the selection circuit 8a is supplied. A bit width adjusting circuit 8b is provided. The selection circuit 8a includes registers 6a, 6
A plurality of outputs from b, 6c, ... Can be selected. In this way, the bit width can be adjusted by allowing a plurality of outputs to be selected at the same time. For example, if two registers are selected at the same time, the data width becomes 2 bytes. Input / output bit width adjustment circuit 8b
Is supplied to one input terminal of the switching circuit 8c. The selection circuit 8 is also included in the second shift circuit 7.
Although similar circuits corresponding to a and the input / output bit width adjusting circuit 8b are provided, they are not shown in FIG.

Next, the operation of the above-mentioned synchronizing circuit 4 will be described.

Consider, for example, the case where the encoded data from the encoding / decoding circuit 2 is stored in the memory circuit 3. In this case, the encoding / decoding circuit 2 serves as an input side device, and the memory circuit 3 serves as an output side device. First, the multiplexer 5 is controlled so that the signal from the encoding / decoding circuit 2 is input and output to the first shift circuit 6. Therefore, the signal from the encoding / decoding circuit 2 is sequentially transferred to the registers 6a, 6b, 6c, ... In the first shift circuit 6. The writing of data to the first shift circuit 6 is performed in synchronization with the shift pulse SP supplied from the shift pulse generating circuit 10 from the encoding / decoding circuit 2 at the timing of the encoding operation. If the data length is m bytes, a necessary amount of data is transferred to the first shift circuit 6 by m transfers. At this time, the switching circuit 8c is switched to the second shift circuit 7 side.

Next, the output side of the multiplexer 5 is switched to the second shift circuit 7 side, and the switching circuit 8c is switched to the first shift circuit 6 side. Then, similarly to the above, the encoded data from the encoding / decoding circuit 2 is sequentially written into the second shift circuit 7. Further, in parallel with the data writing to the second shift circuit 7, the reading of data from the first shift circuit 6 is started. That is, the selection circuit 8a causes the registers 6a, 6b, 6c,
The output of the m-th register is selected from the input side among ... And supplied to the input / output bit width adjusting circuit 8b. The number of register output to be selected is preset by the data length setting circuit 11 according to the data length of the data to be handled. For example, if the data length is 3 bytes, the output of the register 6c is selected. In the input / output bit width adjusting circuit 8b, the bit width of the data is adjusted so that it matches on the input side and the output side, and then supplied to the switching circuit 8c. The input / output bit width adjusting circuit 8b is
This is necessary when the bit widths of the input side device and the output side device are different, but not necessarily required when the bit widths are the same.

The reading of data from the first shift circuit 6 is performed in synchronization with the shift pulse SP supplied from the shift pulse generating circuit 10 at the timing of the write operation of the memory circuit 3. Since the selection circuit 8a selects the output of the m-th register, when m shift pulses SP are supplied to the first shift circuit 6, the m-byte data written in the first shift circuit 6 becomes After all are read and the bit width is adjusted by the input / output bit width adjusting circuit 8b, they are supplied to the memory circuit 3 via the switching circuit 8c and sequentially stored in the memory circuit 3 at a timing synchronized with the shift pulse SP. .

That is, the writing to the second shift circuit 7 is performed in synchronization with the timing of the encoding operation of the encoding / decoding circuit 2, and the reading of the data from the first shift circuit 6 is the writing to the memory circuit 3. It is performed in synchronization with the operation timing. Hereinafter, similarly, the operations of writing to the first shift circuit 6, reading from the second shift circuit 7, writing to the second shift circuit 7, and reading from the first shift circuit 6 are alternately repeated. Therefore, even when the operations of the encoding / decoding circuit 2 and the memory circuit 3 are asynchronous, data can be transferred without any trouble. Also,
By setting in the selection circuit 8a by the data length setting circuit 11 which number of the register output should be selected according to the data length of the data to be handled, data of any data length can be handled.

The above description is for the case where the encoded data from the encoding / decoding circuit 2 is stored in the memory circuit 3, but the encoded data in the memory circuit 3 is encoded / decoded.
The same applies when the data is transferred to and decrypted. In this case, the memory circuit 3 serves as an input side device and the encoding / decoding circuit 2 serves as an output side device.

In the circuit shown in FIG. 2, both the input-side and output-side multiplexers 5 and 9 are connected to the memory circuit 3.
By switching to the side, the data on the memory circuit 3 can be copied to another position of the memory circuit 3.

[0023]

As described above, in the present invention, since the shift circuit in which the number of shifts until the input data is output is variable is used, it is possible to handle data of various data lengths. it can. Further, since the two shift circuits are provided, the write and read operations can be alternately performed, and the data can be transferred even when the input and the output are asynchronous.

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing device to which a synchronization circuit of the present invention is applied.

FIG. 2 is a detailed block diagram showing an internal configuration of a synchronization circuit.

3 is a block diagram showing in further detail the configurations of a first shift circuit and a multiplexer shown in FIG. 2. FIG.

[Explanation of symbols]

1 ... Data input / output circuit, 2 ... Encoding / decoding circuit, 3 ... Memory circuit, 4 ... Synchronization circuit, 5 ... Multiplexer, 6, 7 ...
Shift circuit, 6a, 6b, 6c ... Register, 8, 9 ... Multiplexer, 8a ... Selection circuit, 8b ... Input / output bit width adjusting circuit, 8c ... Switching circuit, 10 ... Shift pulse generating circuit, 11 ... Data length setting circuit

Claims (1)

[Claims] 1. A synchronous circuit, which is provided between an input-side device and an output-side device that are asynchronous with each other and transfers variable-length data from the input-side device to the output-side device, the synchronizing circuit synchronizing with a shift pulse. Two shift circuits in which the number of shifts from data input to output is variable, means for setting the number of shifts in the two shift circuits, and the two shift circuits First selection means for alternately supplying data from the input side device to the circuit, and data from the two shift circuits are alternately selected in a phase opposite to that of the first selection means, and the output side device is selected. Second selection means for outputting to, and a shift pulse synchronized with the timing of the input side device at the time of writing data in the two shift circuits,
And a shift pulse generating means for generating a shift pulse synchronized with the timing of the output side device at the time of reading data from the shift circuit.