JPH0998143A - Data multiplexer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output the data of a bit length not to be limited by the number of multiplexing systems with a reduced memory capacity. SOLUTION: When a bit length K equal with a value obtd. by adding an integer A (0<A<N) to the integer (M) multiple of the number N of systems is designated, data stored in a memory 11, are read out successively from a prescribed pair to the M-th pair in the time cycle of N.T with N bits as a pair. An operation of reading the (M+1)th pair of data at timing of dividing the period of (N+A).T into two periods of more than N.T/2 after the Mth pair of data are read out is repeated at cycles of a K.T time. Synchronously with the reading out of this data from a prescribed pair to the M-th pair, a latch signal is outputted to a latch circuit 14 M times and, an operation of outputting the (M+1)th latch signal at timing of dividing the period of (N+A).T after this M-th latch signal is outputted into the period of A.T and the period of N.T is repeated at cycles of a K.T time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data multiplexer for multiplexing data output in parallel in a plurality of streams by a multiplexer circuit and outputting the multiplexed data as serial data.

[0002]

2. Description of the Related Art For example, in an apparatus for testing a serial line such as a digital communication line, serial data having a predetermined pattern is sent from one end side to the other end side of the line and data received at the other end side. The error rate is measured and the line is evaluated.

When outputting data of a predetermined pattern as described above, it is sufficient to store the pattern data in a memory and read the data from the memory one bit at a time. However, high-speed serial data can be obtained. If necessary, it is necessary to use a high-speed memory capable of reading at an operation speed equivalent to the speed of the serial data. For example, it is extremely difficult to read serial data of several 100 MHz / bit from the memory bit by bit. is there.

In order to solve this problem, conventionally, as shown in FIG. 8, memories 1 ₁ to 1 _N which output data in N series (N is a plurality) and N which is faster than the operating speed of each memory. 2. Description of the Related Art A data multiplexer that uses a 1: 1 multiplexer circuit 2 to time-division-multiplex multiple-sequence data and outputs the multiplexed data is used.

In this data multiplexer, for example, data D [1] to D [NM] in which one pattern is formed with a bit length which is an integer multiple (N · M) of the number of sequences N is T per bit. when the output at the time of the speed, in advance in the memory 1 ₁ data D [1], D [N + 1], ..., D [M (N-1) +
1], in the memory 1 ₂ data D [2], D [N + 2],
..., and so on D [M (N-1) +2], is stored in the memory ₁ 1 to 1 _N divided into N-bit intervals of the data, a read address for the memory ₁ 1 to 1 _N,
Data selection time T per series of the multiplexer circuit 2
N times the cycle.

As a result, from each of the memories 1 ₁ to 1 _N , as shown in FIG. 9A, D [1] to D [N],
D [N + 1] to D [2 · N], D [2 · N + 1] to D
N-bit parallel data is output to the multiplexer circuit 2 every N · T time in the order of [3 · N]. From the multiplexer circuit 2, as shown in (b) of FIG.
Continuous pattern data from [1] to D [NM] is output.

[0007]

However, in the conventional data multiplexing apparatus as described above, there is no problem when the bit length of one pattern that can be output is an integer multiple of the number of sequences N, but it is an integer of the number of sequences N. There is a problem when trying to output data having a bit length that is not double, especially when the bit length is slightly larger than an integral multiple of N.

For example, when outputting a pattern of (N · M + 1) bit length from D [1] to D [N · M + 1],
After reading M sets of N-bit parallel data from D [1] to D [N · M] from the memory at the N · T time period, D
The operation of outputting N-bit parallel data including the [N · M + 1] -th bit data for T time must be repeated.

[0009] However, this memory 1 ₁ must have an operating speed equal to the operation speed of the multiplexer circuit 2, if there is such a high-speed memory, the meaning of multiplexing in the multiplexer circuit It's gone.

To solve this problem, as a method of outputting a pattern having a bit length K that is not an integral multiple of the number of sequences N, data for the least common multiple of the number of sequences N and the bit length K is divided and stored in a memory in advance. It is also possible to save it.

For example, when the number of sequences N is 8 and the bit length of one pattern to be output is 129, the least common multiple thereof is 8 × 129 (= 1032), so that the memories 1 ₁ to
In ₁₈ is stored 1032-bit pattern data in which 129 bits of D [1] to D [129] are consecutive eight times, and this is read out in units of 8 bits.

However, in the method of storing in the memory the data corresponding to the least common multiple of the number of sequences N and the bit length K of the pattern to be output, it takes a very long time to set the data in the memory. In addition, there is a problem in that a very large memory capacity is required compared with the required bit length of one pattern.

It is an object of the present invention to solve this problem and to provide a data multiplexer capable of outputting data having a bit length which is not limited to the number of multiplexing sequences with a small memory capacity.

[0014]

In order to achieve the above object, the data multiplexing apparatus of the present invention is a memory (11 ₁ ) capable of reading stored data in N series in units of N bits (N is a plurality). ~ 11 _N ) and a latch circuit (14 _{1 to} 14 _N ) for latching parallel data read from the memory in N series each time a latch signal is received and outputting the latched parallel data to N series. Each time the parallel data is latched by the latch circuit, the latched parallel data is selected and output in a predetermined order by T time per series from a predetermined series, and the N: 1 multiplexer circuit (12)
A bit length designating means (15) for designating a bit length K of pattern data to be output from the multiplexer circuit; and a bit length K equal to M times (M is an integer) the number of sequences N by the bit length designating means. Is specified, the data stored in the memory is N bit 1
A value obtained by repeating the operation of sequentially reading from a predetermined set in N · T time period as a set in K · T time period, and adding an integer A (0 <A <N) to M times the number of sequences N by the bit length designating means. When a bit length K equal to is designated, the data stored in the memory is set as N bits as one set, and from the predetermined set to M sets in the N · T time cycle, and the Mth set of data is read. M + at the timing of dividing the later (N + A) · T period into two periods of N · T / 2 or more
The read control means (16, 17) that repeats the operation of reading the first set of data in the K · T time cycle and the bit length designating means makes the bit length K equal to M times the sequence number N (M is an integer). Is designated, a latch signal is output to the latch circuit at an N.multidot.T time period, and the bit length designating means makes M an integer A (0 <A <N) times the number N of sequences.
When a bit length K equal to the value obtained by adding
The latch signal is output M times to the latch circuit in synchronism with the data read timing from the predetermined group to the Mth group by the read control means, and the (N + A). T period is AT period and NT period
The latch control means (18) repeats the operation of outputting the (M + 1) th latch signal at the timing divided into the period and the K / T time period.

With this configuration, in the data multiplexing apparatus of the present invention, when the designated bit length K is an integer (M) times the number of sequences N, the data stored in the memory is a set of N bits. As a result, the operation of reading M sets from the predetermined set sequentially in the N · T time cycle is repeated in the K · T time cycle, and the read parallel data is latched by the latch signal of the same cycle as the reading of this data. Therefore, the multiplexer circuit repeatedly outputs the pattern data of N · M bit length at the speed of T time per bit.

When the designated bit length K is larger than A by an integer (M) times the number N of sequences, the data stored in the memory is N bits in one set, and the data is N in order from the predetermined set.
-Up to M sets are read in the T time cycle, and (N + A) -T period after reading the Mth set of data is N-T /
The operation of reading the M + 1th set of data at a timing divided into two or more two periods is repeated in the K · T time cycle, and the latch circuit latches in synchronization with the data read timing from the predetermined set to the Mth set. The operation is performed M times, and the latch operation is performed once more at the timing of dividing the (N + A) .T period after the Mth latch operation is divided into the A.T period and the N.T period. Is repeated in the K · T time cycle, the pattern data of the designated bit length K is repeatedly output from the multiplexer circuit at a speed of T time per bit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a data multiplexing apparatus according to an embodiment.

As shown in FIG. 1, this data multiplexer includes N sets of memories 11 _{1 to} 11 _N , N: 1 multiplexer circuits 12, first latch circuits 13 _{1 to} 13 _N , and second latch circuits 13 _{1 to} 13 _N.
Latch circuits 14 _{1 to} 14 _N , a bit length designating circuit 15,
An address counter 16, a read control circuit 17, and a latch control circuit 18 are provided.

The N sets of memories 11 _{1 to} 11 _N are RAMs capable of reading and writing data, and among the data D previously written by the data writing means (not shown).
The data at the address designated by the address signal from the address counter 16 is output one bit at a time, and N-bit data is output as N series as a whole.

The first latch circuits 13 _{1 to} 13 _N latch the parallel data output from the memories 11 _{1 to} 11 _{N in} N series in synchronization with the read signal R output from the read control circuit 17. , The latched data is the second latch circuit 1
It outputs to N series from 4 _{1 to} 14 _N. The first latch circuits 13 _{1 to} 13 _N are for preventing variations in the data output timing of the memories 11 _{1 to} 11 _N.

The second latch circuits 14 _{1 to} 14 _N form the latch circuit of this embodiment, and latch the parallel data output from the _first latch circuits 13 _{1 to} 13 _{N in} N series. It latches in synchronization with the latch signal L output from the control circuit 18, and outputs the latched data to the multiplexer circuit 12 in N series.

The multiplexer circuit 12 receives the parallel data latched by the second latch circuits 14 _{1 to} 14 _N ,
The latched parallel data is selected and output sequentially from a predetermined series (in this case, from the output data of the second latch circuit 14 ₁ ) by T time per series. In addition,
The time T is the period of the clock signal C, and this clock signal determines the speed of the serial data output from the multiplexer circuit 12 at an extremely high speed (for example, several hundred MH).
z) signal.

The bit length designating circuit 15 is a circuit for designating the bit length K of a series of pattern data to be output from the multiplexer circuit 12.

The address counter 16 constitutes a read control means of this embodiment together with a read control circuit 17 which will be described later. The address counter 16 counts the read signal R output from the read control circuit 17, and the count value is used as an address signal. It is output to the memories 11 _{1 to} 11 _N as AD.

The read control circuit 17 is a bit length designating circuit 1
The generation timing of the read signal is changed depending on whether or not the bit length K designated by 5 is an integer multiple of the sequence number N.

That is, when the designated bit length K is an integer (M) times the number N of sequences, the clock signal C shown in FIG. the operation of outputting M times the read signal at N · T time period until the R ₁ to R _M repeated K · T time period.

Further, when the designated bit length K is equal to a value obtained by adding an integer A (0 <A <N) to the number of sequences N multiplied by an integer (M), as shown in FIG. , The read signal is output M times from R _{1 to} R _M in the N · T time cycle, and the (N + A) · T period after the M-th read signal R _M is output is N · T / 2 or more. The operation of outputting the M + 1th read signal R _P at the timing divided into the two periods Ta and Tb is repeated in the K · T time cycle. Since the shortest cycle of this read signal is N · T / 2 or more, each memory ₁₁ to
The operating speed of 1 _N may correspond to this period. Further, the address counter 16 receives the first read signal R
_The address signal is set to have an initial value SD ₁ when it receives ₁ .

On the other hand, similarly to the read control circuit 17, the latch control circuit 18 changes the generation timing of the latch signal depending on whether or not the bit length K designated by the bit length designation circuit 16 is an integer multiple of the sequence number N. .

That is, when the designated bit length K is an integer (M) times the number of sequences N, as shown in (d) of FIG.
The operation of the latch signal synchronized with the read signal R ₁ to R _M to M-th output M times until L ₁ ~L _M repeated K · T time period.

If the designated bit length K is equal to the number of sequences N multiplied by an integer (M) times the integer A, as shown in FIG. Signal R ₁ ~
A latch signal synchronized with the R _M outputs M times until L ₁ ~L _M, after the output of the latch signal of the M-th (N + A)
・ T period is 2 period Tc of A ・ T time and N ・ T time,
At the timing of dividing into Td, the M + 1th latch signal L _P
Is output in the K · T time cycle.

Next, the operation of the data multiplexer having the above configuration will be described. Here, the number of sequences N is 8 and the designated bit length K is 128 bits (16 times the number of sequences N).
And the case of 129 bits (a value obtained by adding 1 to twice the number of sequences N) will be described.

When the designated bit length K is 128 bits, as shown in FIG. 3, the data D [1] to D [128] to be output are divided into 8 bits and stored in the memory 11 _1. It is stored in the addresses AD _{1 to} AD ₁₆ of ˜11 ₈ .

Then, the read control circuit 17, as shown in FIG. 4A, is 16 times (M times) in the 8 · T time period.
The operation of outputting the read signals R _{1 to} R ₁₆ is repeated. The address counter 16 receiving this read signal outputs the address AD ₁ when receiving the first read signal R ₁ , and increments the address each time the read signal is received thereafter.

Therefore, from the memories 11 _{1 to} 11 ₈ , as shown in FIG. 4B, D [1] to D [12]
8], 16 sets of 8-bit data are output in sequence every 8 · T time.

This 8-bit data is latched by the first latch circuits 13 _{1 to} 13 ₈ in synchronization with the read signal, as shown in FIG.
As shown in (c) of FIG.

The latch outputs of the first latch circuits 13 _{1 to} 13 ₈ are read signals R ₁ to R ₁ as shown in FIG. 4D.
The latch signals L _{1 to} L ₁₆ synchronized with R ₁₆ are latched by the second latch circuits 14 _{1 to} 14 ₈ and further delayed by 8 · T time as shown in FIG.
Will be entered in.

Therefore, as shown in FIG. 4 (f), the multiplexer circuit 12 outputs D [1] to D [12].
8] continuous pattern data of 128 bit length,
It is repeatedly output at a speed of T time per bit.

When the designated bit length K is 129 bits, the data D among the data D [1] to D [129] to be output is previously stored as shown in FIG.
The data from [1] to D [128] are stored in the addresses AD _{15 to} AD ₁₇ and AD _{1 to} AD ₁₃ of the memories 11 _{1 to} 11 ₈ in units of ₈ bits, and the 129th bit data D [129] is stored. ] Is stored in the address AD ₁₄ of the memory 11 ₁ . The data D [130] to D [136] are invalid data.

Then, as shown in FIG. 6A, the read control circuit 17 outputs the read signals from R _{1 to} R ₁₆ to 8 · T.
An operation of outputting 16 times in a time cycle and then outputting the 17th read signal R _P at the timing of dividing the subsequent (8 + 1) · T period into, for example, two periods Ta and Tb of 5 · T time and 4 · T time. Is repeated every 129 · T time period. The address counter 16 outputs the address AD ₁ when receiving the first read signal R ₁ , and increments the address each time the read signal is received thereafter.

Therefore, from each of the memories 11 _{1 to} 11 ₈ , as shown in FIG. 6B, D [25] to D [8]
Up to 15 sets of 8-bit data are output in 8 · T time interval, and then D

A set of 8-bit data from [9] to D [16] is output for 4 · T time, and then D
One set of 8-bit data from [17] to D [24] is 5
・ The operation of outputting for T time is repeated.

Since this read signal is input to the first latch circuits 13 _{1 to} 13 ₈ as a latch signal, the first latch circuits 13 _{1 to} 13 _N are shown in FIG. 6 (c). As shown, for the data in (b) of FIG.
Data delayed by one read signal is output. That is, the first
Latch circuits 13 _{1 to} 13 ₈ of D [17] to D [13
6] to 15 sets of 8-bit data are output in sequence for 8 · T time, and then a set of 8 sets of D [1] to D [8]
Outputs bit data for 4T time, then D

[9] ~
The operation of outputting a set of 8-bit data up to D [16] for 5 · T time is repeated at 129 · T time cycle.

On the other hand, the latch control circuit 18 outputs the latch signals L _{1 to} L ₁₆ synchronized with the read signals R _{1 to} R ₁₆ and then (8 + 1) thereafter, as shown in FIG. 6D.
The operation of outputting the latch signal L _P at the timing of dividing the T period into T time and 8 · T time is repeated in the 129 · T time cycle.

Therefore, the second latch circuits 14 ₁ to ₁ 1
As shown in (e) of FIG. 6, 4 ₈ is 128 · from the generation of the latch signal L _P to the generation of the latch signal L _16.
16 sets of 8-bit data D [1] to D [128] are output at T time, and one set of data D [12] is output at T time from the generation of the latch signal L ₁₆ to the latch signal L _P.
9] to D [136] are repeatedly output.

For this reason, the 8: 1 multiplexer circuit 1
From 2 onward, as shown in (f) of FIG.
Continuous 129-bit pattern data up to D [129] is repeatedly output at a speed of T time per bit.

As described above, even when the multiplexer circuit 12 has the worst condition of continuously selecting data from the same series, the data read interval to the memory is significantly longer than the data selection cycle T of the multiplexer circuit 12. Can be late.

Further, since it is sufficient to store the data for one pattern of the pattern to be output in the memory, a method for storing the data for the least common multiple of the bit length K and the number of sequences N of the required pattern can be stored. In comparison, the memory capacity is much smaller, and the time required to store data in the memory can be significantly reduced.

Further, since the data read-out cycle to the memory is set to N.multidot.T / 2 or more, the operation speed required for the memory itself should be one that can cope with the access of N.multidot.T / 2 time cycle. Better, it doesn't have to be much faster. For example, the number of sequences N is 8 and the data selection period T of the multiplexer circuit 12 is 5 nS (200 MHz).
Then, N · T / 2 becomes 20 nS, and this speed cannot be said to be exceptionally high with the current technology, and can be sufficiently realized.

Although FIG. 6 illustrates the operation when the designated bit length K is larger than the integral multiple of the number of sequences N by 1 (A = 1), the value of A is 2 or more. (N-1)
In the following cases, the time from the Mth latch signal (L ₁₆ ) to the M + 1th latch signal (L _P ) is only extended to the A / T time, and other operations are performed as shown in FIG. Since it is the same as that from the multiplexer circuit 12,
The pattern data of + A) bit length is repeatedly output, and the bit length of the pattern to be output can be arbitrarily specified at 1-bit intervals.

When pattern data having a bit length smaller than the number of sequences N is to be output (when M is 0), the K-bit data to be output should be kept output from the memory at all times. Every other time, if the read signal and the latch signal are synchronously output in the A / T time cycle, a pattern of bit length K can be output.

[0050]

Other Embodiments In the above-described embodiment, the data output from the memory is temporarily latched by the first latch circuits 13 _{1 to} 13 _N , and the latch output is latched by the second latch circuits 14 _{1 to} 14 _{N. Although} it is latched by N and output to the N: 1 multiplexer circuit 12, the first latch circuits 13 _{1 to} 13 _N may be omitted as shown in FIG. 7. In this case, the initial setting of the address counter 16 may be delayed by one address.

For example, as described above, when the number of sequences N is 8 and the bit length K is 129, the address counter 16 receiving the read signal R ₁ outputs the address AD ₁₇ and the address receiving the read signal R ₂ is received. The counter 16 outputs the address AD ₁ and ..., The address counter 1 which receives the read signal R _P
If 6 is set to output address AD ₁₆ ,
The memories 11 _{1 to} 11 ₈ output the same data at the same timing as the first latch circuits 13 _{1 to} 13 ₈ shown in FIG. 6C, and the multiplexer circuit 12 outputs D [1] to D It is possible to output continuous pattern data up to [129].

[0052]

As described above, in the data multiplexing apparatus of the present invention, the latch circuit is provided between the memory and the N: 1 multiplexer circuit, and the integer A is multiplied by an integer (M) times the number of sequences N. When a bit length K equal to a value obtained by adding (0 <A <N) is designated, the data stored in the memory is read as a set of N bits from the predetermined set to M sets in the N · T time cycle. , The operation of reading the data of the M + 1th group is repeated at the timing of dividing the (N + A) · T period after reading the Mth group of data into two periods of N · T / 2 or more in the K · T time cycle. At the same time, the latch signal is output M times to the latch circuit in synchronization with the data read timing from the predetermined group to the Mth group, and the (N + A) · T period after the Mth latch signal is output is A・ T
The operation of outputting the (M + 1) th latch signal at the timing divided into the period and the N · T period is repeated in the K · T time period.

Therefore, pattern data having an arbitrary bit length K can be output without being limited to the number N of sequences.
Moreover, since it is sufficient to store only the data of the specified bit length in the memory, the capacity of the memory can be small and the time for writing data to the memory can be short.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing diagram showing a difference in output timing between a read signal and a latch signal for a specified bit length according to an embodiment.

FIG. 3 is a diagram showing an example of data stored in a memory according to an embodiment.

FIG. 4 is a timing chart when outputting a pattern having a bit length that is an integer multiple of the number of sequences N.

FIG. 5 is a diagram showing an example of data stored in a memory according to an embodiment.

FIG. 6 is a timing chart when outputting a pattern having a bit length that is not an integer multiple of the number of sequences N.

FIG. 7 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional device.

FIG. 9 is a timing chart showing the operation of the conventional device.

[Explanation of symbols]

11 _{1 to} 11 _N memory 12 multiplexer circuit 14 _{1 to} 14 _N second latch circuit 15 bit length designation circuit 16 address counter 17 read control circuit 18 latch control circuit

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[Procedure amendment]

[Submission date] November 16, 1995

[Procedure Amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

[Fig. 2]

[Figure 3]

FIG. 4

[Figure 5]

FIG. 6

[Figure 8]

[Figure 9]

FIG. 7

Claims (1)

[Claims] 1. Data stored in N-bit units (N
Is a plurality of) and a memory (11 ₁ to ₁ ) capable of reading in N series.
1 _N ) and parallel data read out in N series from the memory every time a latch signal is received, and a latch circuit (14 _{1 to} 14 _N ) for outputting the latched parallel data in N series.
An N: 1 multiplexer circuit (12) for selecting and outputting the latched parallel data in a predetermined order by T time per series from the predetermined series every time the parallel data is latched by the latch circuit; Bit length specifying means (1) for specifying the bit length K of the pattern data to be output from the multiplexer circuit.
5) and when a bit length K equal to M times (M is an integer) the number of sequences N is designated by the bit length designating means, the data stored in the memory is regarded as one set of N bits in order from a predetermined set. The operation of reading in the N · T time cycle is performed in K ·
When the bit length K is designated by the bit length designating means and is equal to a value obtained by adding an integer A (0 <A <N) to M times the number of sequences N, the bit length K is stored in the memory. Data is read as one set of N bits in sequence from the predetermined set to M sets at the N · T time cycle, and (N + A) · T period after reading the Mth set of data is N · T /
The read control means (16, 17) which repeats the operation of reading the M + 1th set of data at a timing divided into two or more two periods in the K · T time cycle, and the bit length designating means makes M times the sequence number N ( When a bit length K equal to (M is an integer) is designated, a latch signal is output to the latch circuit at an N · T time period, and the bit length designating means makes an integer A (0 <0 <M times the sequence number N).
When a bit length K equal to a value obtained by adding A <N) is designated, a latch signal is output M times to the latch circuit in synchronization with the data read timing from the predetermined group to the Mth group by the read control means. Then, the operation of outputting the M + 1th latch signal at the timing at which the subsequent (N + A) · T period is divided into the A · T period and the N · T period after the Mth latch signal is output, A data multiplexer comprising a latch control means (18) which repeats in a T time period.