JP3198709B2 - Data write and read circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data write and read circuit which operates to write data once and then read the data by using a synchronized write synchronization signal and read synchronization signal. In a data communication line of a speed or a different speed, data writing and data suitable for transferring data every n bits from one data communication line to another data communication line or from an external data source to a certain data communication line. This is for a read circuit.

[0002]

2. Description of the Related Art With the advancement of communication technology, for example, it has become necessary to transfer data from one communication line having a different data transfer speed to another communication line.
Various networks can be constructed by combining various communication lines, and facilities and information resources can be shared.

When data is transferred between such different lines, it is necessary to insert the data to be transferred into the destination communication line after the data to be transferred is converted into a suitable format.
Conventionally, an elastic memory, which is a dedicated IC, has been used for such a purpose for temporary storage.

Next, FIG. 5 shows the configuration of an elastic memory. In FIG. 5, an elastic memory 71 is a memory capable of asynchronously performing writing and reading of data, receives a write data Din and a write clock WCK, and writes the written data in accordance with the write clock WCK. It is shifted sequentially in the memory. In the elastic memory 71, the read signal R
The data written according to S is read. The read timing control circuit 72 to which the read synchronization signal RSS and the read clock RCK are input receives the read signal R
S is generated, and the read signal RS is set with a delayed input timing according to the data length possessed by the elastic memory, and can be set freely.

Since writing and reading can be performed asynchronously in the elastic memory 71, data can be easily inserted into another communication line or the like by reading out the clock at the location where the written data is inserted.

[0006]

When the data transfer speed is converted and transferred, the circuit can be simplified by using the elastic memory 71 which is a dedicated LSI.

However, elastic memories are considerably more expensive than general-purpose memories, and as a result, the product unit price may increase. Further, the elastic memory itself has a problem of the operation speed, and at the same time, has a surplus function and the like, so that the usability for the user is not always good.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data write and read circuit which performs similar signal processing without using a dedicated LSI and realizes reliable data write and read.

[0009]

[MEANS FOR SOLVING THE PROBLEMS] The input data is serial /
An input data sending means for sending to convert the block data by parallel conversion, in order to achieve this object, in this invention, serial input data by the input data transmission means
This data is converted to block data by
The lock data is sent to the data shift means , and the block data is stored while being sequentially shifted by the data shift means by the write synchronization signal. Further, the write synchronization signal and the read synchronization signal synchronized with each other are supplied to pointer control means, where a pointer signal corresponding to the phase relationship between the synchronization signals is generated. Data read means operates to read the block data in the specified data shift means by the pointer signal read
The output block data is output to output means. Soshi
The output means outputs the block data in parallel /
It is converted to serial data by serial conversion and output.

The data reading means can be constituted by a buffer memory corresponding to the number of shifts, and the buffer memory can be designated by a pointer signal.

[0011]

When data write control and data read control are performed by a write synchronizing signal and a reading synchronizing signal synchronized with each other, reference pulses basically appear alternately. In consideration of the case where the jitter or the like is superimposed, it is not always constant but changes, and the reference pulse of the write synchronization signal does not always follow the reference pulse of the read synchronization signal. Therefore, in the data writing and reading circuit of the present invention, writing is sequentially performed by the data shift means so that the data can be read reliably even if the phase relationship of the synchronization signal is broken. Thus, even if a shift operation occurs, the pointer is controlled so that appropriate data is steadily read out by the pointer, and even when reading is continued, redundant reading is avoided.

[0012]

FIG. 1 shows the configuration of an embodiment according to the present invention.
This will be described with reference to FIGS. In FIG. 1, a data write / read circuit 7 includes an input circuit 1 for handling data, a data shift circuit 2, a data read circuit 3 and an output circuit 6, and a write / read control circuit 2 for controlling these and a read / write control circuit 2, respectively. A pointer control circuit 5 is provided.

The input circuit 1 sequentially shifts the write data Din by write data (insertion data) Din, a write clock WCK, and a write synchronization signal WSS, and latches the data every n bits. The output of the input circuit 1 is a data block for every n bits.

The data shift circuit 3 stores data in data block units while sequentially shifting a data block of n bits in accordance with the write synchronization signal WSS. Here, the write synchronization signal WSS indicates that the data block is n
If it is bit by bit, the signal is a signal in which the reference pulse appears once every n clocks of the write clock WCK. Each data block is shifted at the timing of the reference pulse of the write synchronization signal WSS.

The data read circuit 4 is a circuit for reading a data block designated by a pointer of the read pointer control circuit 5 and outputting the read data block to the output circuit 6. Each data block of the data shift circuit 3 is always read by the data read circuit 4, and any data block can be read by designating a pointer.

The output circuit 6 converts the read data block from parallel to serial to read clock R.
This is a circuit that outputs to the outside according to the timing of CK.
The read clock RCK is equal to the write clock WC.
A clock faster than K can be selected, and data can be inserted into a higher-speed communication line.

The write / read control circuit 2 uses the write synchronizing signal WSS and the read synchronizing signal RSS to
A signal to the data shift circuit 3 and the read pointer control circuit 5 is created. The write synchronizing signal WSS and the read synchronizing signal RSS are synchronized signals, but when the timings of the two overlap due to a phase shift, priority control between the two is performed, and the operation based on both signals is reliably performed. Will be

The read pointer control circuit 5 counts up the counter by one when receiving the write synchronizing signal WSS from the write / read control circuit 2, and conversely, when receiving the read synchronizing signal RSS from the write / read control circuit 2, Is counted down by one. When the phases of the write synchronizing signal WSS and the read synchronizing signal RSS are the same, up-counting and down-counting are alternately repeated, and up-down is repeated around a pointer designating the reference (0). . A pointer is determined based on the value of the counter, and a data block to be read by the data read circuit 4 is determined based on the determined pointer.

If the phase relationship between the read synchronizing signal RSS and the write synchronizing signal WSS is broken and the write synchronizing signal WSS is detected continuously, data is read using the pointer designating the reference + α. , Follows the shift operation in the data shift circuit 3, and no data loss occurs. Conversely, even when the read synchronizing signal RSS is continuously detected, data is read from the pointer designating the reference -α, and redundant reading of data does not occur.

Next, a circuit configuration for inserting 8-bit data according to the present invention will be described with reference to FIG. As the input circuit 1, an S / P (serial / parallel) conversion circuit 11 is used, and write data Din is input. The input write data Din is sequentially shifted by the write clock WCK, latched every eight bits at the timing of the pulse of the write synchronization signal WSS, and formed into an 8-bit data block.

The data shift circuit 3 has five stages of 8-bit latch circuits 31 to 35 connected in series, and an 8-bit parallel input / output is performed between them. The data from the S / P conversion circuit 11 is input to the latch circuit 31, and is sequentially transmitted to the next-stage latch circuit for each 8-bit data block at the timing of the pulse of the write synchronization signal WSS. In the last-stage latch circuit 35, the pointer from the read pointer setting circuit 52
Output is performed only when is specified. Among the five-stage latch circuits 31 to 35, for example, the middle latch circuit 3
3 is selected as a reference latch circuit, and reading can be performed based on the latch circuit 33 as a reference.

The data read circuit 4 comprises four buffer circuits 41 to 44. The buffer circuit 41 is used for reading the first-stage latch circuit 31, and the buffer circuit 42 is used for reading the next-stage latch circuit 32. Reference numeral 43 is used for reading data from the third-stage latch circuit 33, and buffer circuit 44 is used for reading data from the fourth-stage latch circuit 34. One of the buffer circuits 41 to 44 and the latch circuit 35 is selected by the designation of the pointer sent from the read pointer setting circuit 52,
The circuit outputs the held 8-bit block data to a P / S (parallel / serial) conversion circuit 61 which is an output circuit 6.

The P / S conversion circuit 61 converts the received 8-bit data block into serial data, and sends output data Dout to a desired communication line or the like according to the read clock RCK. The read clock RCK may be faster than the write clock WCK.

The write / read control circuit 2 comprises a write synchronization signal detection circuit 21, a read synchronization signal detection circuit 22, and a phase adjustment circuit 23. Write synchronization signal detection circuit 21 and read synchronization signal detection circuit 22
Detects the write synchronizing signal WSS and the read synchronizing signal RSS, respectively, and converts the detected signals to the phase adjustment circuit 2.
Send to 3. The phase adjustment circuit 23 is an arbitration circuit that performs an arbitration operation when a pulse of the write synchronization signal WSS and a pulse of the read synchronization signal RSS coincide with each other.
For example, control is performed so that the read-side pulse is prioritized, and then the write-side pulse is transmitted. The write synchronization signal WSS and the read synchronization signal RSS after the phase adjustment are both sent to the up / down counter 51, and the write synchronization signal WSS is supplied to the latch circuits 31 to 35.
The read synchronizing signal RSS is also supplied to the P / S conversion circuit 61.

The up / down counter 51 performs 1-bit up-counting by inputting the pulse of the write synchronizing signal WSS after the phase adjustment, and similarly performs 1-bit down-counting by inputting the pulse of the read synchronizing signal RSS. The result is sent to the read pointer setting circuit 52. In this read pointer setting circuit 52,
A pointer is set according to the count value of the up / down counter 51, and the buffer circuit 41
To 44 or one of the latch circuits 35.

Next, the operation of the circuit of FIG. 2 will be described with reference to FIG. At the timing of the pulse of the write synchronizing signal WSS after the phase adjustment by the phase adjustment circuit 23, the data latched in the latch circuits 31 to 35 is shifted, and as shown in FIG. For example, it is counted up from the initial value 7 to the value 8. As a result, the designation of the pointer, for example, the designation of the reference buffer circuit 43 replaces the designation of the buffer circuit 44, and follows the data shift even when the reading is continued.

Next, when a pulse of the read synchronizing signal RSS is detected, the count value of the up / down counter 51 is counted down from 8 to 7, and the newly input data is read so that the same data is not read a plurality of times. Shift the pointer specification to the block side. The reference buffer circuit 43 is again selected as the read buffer by the designation of the pointer, and the pulse of the read synchronizing signal RSS causes
Reading to the P / S conversion circuit 61 starts.

Normally, the write synchronizing signal WSS and the read synchronizing signal RSS are alternately input, so that the count value of the up / down counter 51 is within a range of +1 or -1 with respect to the initial value set in the counter. Up-counting and down-counting are repeated. if,
When the write synchronizing signal WSS is detected twice consecutively due to the phase shift, the up / down counter 51 is also set to 2
The count is continuously performed every time, and the buffer circuit 44 (and the latch circuit 35) is used for reading. Conversely, when the read synchronizing signal RSS is detected twice consecutively, the up / down counter 51 also counts down twice consecutively, the count value decreases to 6, and the buffer circuit 42 is used for reading. Is done. By changing the data read buffer in accordance with the state of the write / read signal in this way, the data write / read circuit of this embodiment constitutes a kind of elastic memory and realizes data insertion.

FIG. 3 is a diagram showing the signal formats of both communication lines when data is inserted. This figure is 64K
This shows a case where b / s data is inserted into the third channel of a 2048 Kb / s frame. Thus 204
If data is to be inserted into the third channel of the 8 Kb / s frame, by using the read clock RCK as a clock only at the CH3 position, insertion into a communication line of a different speed is surely executed. In the case of 64 Kb / s data, the write synchronization signal WSS and the read synchronization signal RSS are signals having a frequency of 8 kHz.

[0030]

According to the present invention, data can be written and read without using a dedicated IC, and the cost of the product can be reduced by using this circuit for a part of various products. Can be. In particular, data can be easily inserted into different communication lines, and no data is dropped or duplicated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data write and read circuit according to the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a diagram showing an example of a data format of two communication lines showing an example of data insertion.

FIG. 4 is a waveform chart for explaining the operation of the circuit of FIG. 3;

FIG. 5 is a diagram showing an elastic memory used for conventional data insertion.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input circuit 2 write / read control circuit 3 data shift circuit 4 data read circuit 5 read pointer control circuit 6 output circuit 11 S / P conversion circuit 23 phase adjustment circuit 31-35 latch circuit 41-44 buffer circuit 51 up / down counter 52 read Pointer setting circuit 61 P / S conversion circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/00 H04L 13/08

Claims (2)

(57) [Claims] 1. A data writing and reading circuit for reading data after writing data by using a write synchronization signal and a read synchronization signal which are synchronized with each other, converts input data into block data by serial / parallel conversion, and sends the block data. Input data sending means, data shift means for storing the block data while sequentially shifting the block data according to the write synchronization signal, and pointer control means for outputting a pointer signal corresponding to a phase relationship between the write synchronization signal and the read synchronization signal. When a data reading means for reading the block data in the specified data shift means by said pointer signals, the block data read out by the data reading means Pas
Output means for converting the data into serial data by parallel / serial conversion and outputting the serial data . 2. A data writing and reading circuit according to claim 1, wherein said data reading means has a buffer memory corresponding to the number of shifts, and said buffer memory is designated by a pointer signal. Write and read circuits.