JP2593017B2 - Serial data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data transfer device provided with a parallel-serial conversion circuit used on the transmission side in serial data transfer.

[0002]

2. Description of the Related Art As a data transfer method between ICs, serial transfer is more advantageous than parallel transfer in terms of the number of pins and the number of wires.
, Serial transfer is often used for PCM data transfer between the signal processing IC and the AD converter and DA converter ICs.

FIG. 3 is a timing chart showing an example of transfer timing which should be satisfied by a serial data transfer device on the transmission side. In the figure, CLK is a transfer clock pulse, and S is n-bit serial data to be transferred. Also, L
R is a word signal as a control signal indicating a channel attribute or the like, and in the example shown in FIG. 3, both the rising edge and the falling edge indicate the timing of a break of one word of the serial data S to be transferred. ing. In general,
The word signal LR is a binary logical signal of “0” and “1”, and one word of the serial data S to be transferred is determined when at least one of the rising edge and the falling edge is a significant edge. Indicates the timing of the break. Then, the serial data S is required to be sequentially transferred in synchronization with the clock pulse CLK so that all the bits fall exactly between two adjacent significant edges of the word signal LR.

FIG. 4 shows a block diagram of a conventional serial data transfer device according to the transfer timing shown in FIG. In the figure, 31 is a parallel / serial conversion circuit (P / S) for converting parallel data P into serial data S, and 32 is a clock pulse CLK with B as a count initial value.
Is a clock pulse counting circuit (COU) for counting. Both the load signal LD supplied through the load signal input terminal 21 and the clock pulse CLK supplied through the clock pulse input terminal 22 are both a parallel / serial conversion circuit (P / S) 31 and a clock pulse counting circuit (COU) 32. Are applied in common. The serial data S is converted to a parallel / serial conversion circuit (P / S) 31.
Is output through a serial data output terminal 23, and a word signal LR is output from a clock pulse counting circuit (COU) 32.
From the control signal output terminal 24.

The operation of the serial data transfer device of FIG. 4 having the above configuration will be described with reference to a timing chart shown in FIG. FIG. 5 illustrates a specific example of the operation when the number of bits per word of the serial data S to be transferred, that is, the word length is 8 bits.

First, when a load signal LD is supplied, the parallel data P is converted into a parallel / serial conversion circuit (P / S).
Simultaneously with the loading into 31, the binary representation value "7" of the word length of the serial data S to be transferred is set as a positive count initial value B in the clock pulse counting circuit (COU) 32 (B = 7). . Thereafter, the parallel / serial conversion circuit (P / S) 31 immediately shifts the loaded parallel data P one bit at a time in synchronization with the clock pulse CLK, and sequentially outputs the result of the bit shift as serial data S. On the other hand, a clock pulse counting circuit (C
OU) 32 counts down the clock pulse CLK and inverts (rises) the polarity of the word signal LR when the count value becomes negative. Thereby, the clock pulse C
Transfer timing according to FIG. 3 is obtained between LK, word signal LR, and serial data S.

[0007]

The above conventional serial data transfer device has a clock pulse counting circuit (COU) 3
Since the polarity inversion timing of the word signal LR is determined based on the count value of 2, the polarity inversion position of the word signal LR output from the clock pulse counting circuit (COU) 32 determines the parallel data P in parallel. It changes according to the position of the load signal LD for loading the serial conversion circuit (P / S) 31 and setting the count initial value B in the clock pulse counting circuit (COU) 32. For example, the load signal L is applied to the falling edge of the word signal LR.
If the timing of D is delayed, the rise of the word signal LR is delayed accordingly. When the load signal LD is under program control, the phase of the word signal LR changes depending on the program. The serial data S
, The phase of the word signal LR changes. For example, when the word length becomes long, the rising of the word signal LR is also delayed by that much. Further, when the phase of the word signal LR changes as described above, the clock pulse CL occupying within one cycle of the word signal LR.
The number of K pulses, that is, the frequency ratio between the clock pulse CLK and the word signal LR also changes.

As described above, in the conventional serial data transfer device, the phase of the word signal LR changes in accordance with the position of the load signal LD and the word length of the serial data S, so that the clock pulse CLK and the word signal L
Since the frequency ratio between R and R changes, there is a problem that the flexibility of system design is greatly impaired in the application of connecting several ICs to each other by a serial transfer method.

An object of the present invention is to keep the frequency ratio and the phase relationship between the clock pulse CLK and the word signal LR constant while keeping all bits of the serial data S at two adjacent significant edges of the word signal LR. Between the serial data S and the clock pulse CL
An object of the present invention is to provide a serial data transfer device capable of sequentially transferring data in synchronization with K.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, according to the present invention, a conventional word signal L is applied.
In this configuration, the shift timing of the parallel-serial conversion circuit is determined by controlling the operation of the clock pulse counting circuit based on R and the clock pulse CLK.

More specifically, the invention of claim 1 is:
The number of clock pulses CLK during the period when the word signal LR has a first logical value (eg, “0”) and the number of clock pulses CLK during the period when the word signal LR has a second logical value (eg, “1”) This relates to the case where the number of clock pulses CLK coincides with each other. As shown in FIG. 1, the following edge detection circuit 11, first clock pulse counting circuit (COU1) 13, and second clock pulse counting are performed. Circuit (C
OU2) 14 and parallel / serial conversion circuit (P / S) 1
2 is adopted. That is, the edge detection circuit 11 is a binary logic signal, and at least one of the rising edge and the falling edge is a significant edge indicating the timing of a break of one word of the serial data S to be transferred. The edge detection signal a is output each time the signal LR is supplied and a significant edge of the word signal LR is supplied. The first clock pulse counting circuit (COU1) 13 sets a value indicating the number of bits per word of the serial data S to be transferred at the time when the edge detection signal a from the edge detection circuit 11 is supplied to the count initial value. The count value is sequentially changed in a predetermined direction in synchronization with the clock pulse CLK until it is set as B1 and the next time the edge detection signal a is given from the edge detection circuit 11. The second clock pulse counting circuit (COU2) 14 receives the edge detection signal a from the edge detection circuit 11 and supplies the first clock pulse counting circuit (COU2) at that time.
1) The count value before the initial setting of 13 is set as the count initial value B2, and the clock pulse C is used until the edge detection signal a is given from the edge detection circuit 11 next time.
LK, the first clock pulse counting circuit (CO
U1) The count value is sequentially changed in the direction opposite to the direction 13. The parallel / serial conversion circuit (P / S) 12
When the edge detection signal a from the edge detection circuit 11 is given, the parallel data P to be converted into the serial data S is loaded, and then the edge detection circuit 11
Until the edge detection signal a is given, the bit shift of the loaded parallel data P synchronized with the clock pulse CLK is started under the control of the count value of the second clock pulse counting circuit (COU2) 14. Then, the result of the bit shift is sequentially output as serial data S.

[0012] Further, according to the invention of claim 2, the word signal LR
Of the clock pulse CL during the period in which
It is possible to cope with the case where the number of pulses of K does not match the number of clock pulses CLK during a period in which the word signal LR has the second logical value. In the configuration including the first and second clock pulse counting circuits and the parallel-serial conversion circuit, storage for selectively storing the count value of the first clock pulse counting circuit according to the logical value of the word signal LR. In this configuration, a circuit is provided between a first clock pulse counting circuit and a second clock pulse counting circuit. In other words, the edge detection circuit is provided with a word signal LR which is a binary logic signal, in which both the rising edge and the falling edge are significant edges indicating a break of one word of serial data to be transferred, and The edge detection signal a is output every time a significant edge of the word signal LR is given. When the edge detection signal a from the edge detection circuit 11 is supplied, the first clock pulse counting circuit outputs one of the serial data to be transferred.
A value indicating the number of bits per word is set as a count initial value B1, and the count value is sequentially incremented in a predetermined direction in synchronization with the clock pulse CLK until the edge detection signal a is supplied from the edge detection circuit. To change it. The storage circuit stores the count value before the initial setting of the first clock pulse counting circuit at the time from when the edge detection signal a corresponding to the rising edge of the word signal LR is given from the edge detection circuit. While the first clock value is held as the first stored value, the time from when the edge detection signal a corresponding to the falling edge of the word signal LR is given to the time before the initial setting of the first clock pulse counting circuit at that time. The counted value is held as a second stored value separately from the first stored value. The second clock pulse counting circuit includes:
When an edge detection signal a corresponding to a rising edge of the word signal LR is supplied from the edge detection circuit, a second storage value of the storage circuit is set as a count initial value B2 while the word signal LR When the edge detection signal a corresponding to the falling edge is given, the first storage value of the storage circuit is set as the count initial value B2 instead of the second storage value of the storage circuit, and Until the time when any one of the edge detection signals a is supplied from the edge detection circuit, the count value in the direction opposite to that of the first clock pulse count circuit is synchronized with the clock pulse CLK based on each count initial value B2. Are sequentially changed.
The parallel-serial conversion circuit is loaded with the parallel data P to be converted to serial data S at the time when the edge detection signal a from the edge detection circuit is supplied, and then supplies the edge detection signal a from the edge detection circuit. Until this time, the bit shift of the loaded parallel data P in synchronization with the clock pulse CLK is started under the control of the count value of the second clock pulse counting circuit, and the result of the bit shift is transmitted to the serial data S. Are sequentially output.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the first clock pulse counting circuit (COU1) 13 outputs one of the serial data S to be transferred.
The second clock has a function of sequentially increasing the count value in synchronization with the clock pulse CLK after a negative value obtained by expressing the binary representation value of the number of bits per word in two's complement is set as the count initial value B1. Pulse counting circuit (COU
2) 14 has a function of sequentially decreasing the count value in synchronization with the clock pulse CLK, and the parallel / serial conversion circuit (P / S) 12 has a negative count value of the second clock pulse count circuit (COU2) 14. , Each of which has a function of starting the bit shift of the parallel data P.

According to a fourth aspect of the present invention, in the first or second aspect of the present invention, the first clock pulse counting circuit (COU1) 13 outputs one of the serial data S to be transferred.
The clock pulse CLK after the binary representation of the number of bits per word has been set as the positive count initial value B1.
The second clock pulse counting circuit (COU2) 14 has a function of sequentially increasing the count value in synchronization with the clock pulse CLK, and a function of sequentially decreasing the count value in synchronization with the parallel-serial conversion circuit (P / S) 12 employs a configuration having a function of starting the bit shift of the parallel data P after the count value of the second clock pulse counting circuit (COU2) 14 becomes positive.

[0015]

According to the first aspect of the present invention, the parallel-serial conversion circuit (P / S) 12, the first clock pulse counting circuit (COU1) 13, and the second clock pulse counting circuit (COU2) 14 in FIG. The frequency ratio and the phase relationship between the clock pulse CLK commonly applied to the clock signal and the word signal LR applied to the edge detection circuit 11 are determined in advance, and indicate a word indicating the timing of a break of one word of the serial data S. The shift operation of the parallel / serial conversion circuit (P / S) 12 and the first and second clock pulse counting circuits (COU1, COU1) are performed according to the position of the significant edge of the signal LR.
2) The counting operations of 13 and 14 are controlled.

That is, first, the edge detection circuit 11 outputs an edge detection signal a every time a significant edge of the word signal LR is given. Parallel-serial conversion circuit (P /
In step S) 12, the parallel data P is loaded when the edge detection signal a from the edge detection circuit 11 is supplied, but the bit shift of the loaded parallel data P is not immediately started. The bit shift starts only when the count value of the second clock pulse counting circuit (COU2) 14 satisfies a predetermined condition.

On the other hand, when the edge detection signal a is given, the count initial value B1 set in the first clock pulse counting circuit (COU1) 13 is the number of bits per word of the serial data S to be transferred, that is, the word. The count initial value B2 set in the second clock pulse counting circuit (COU2) 14 when the edge detection signal a is applied is the value indicating the length. 1
Of the clock pulse counting circuit (COU1) 13 before the initialization. In addition, the first clock pulse counting circuit (COU1) 13 and the second clock pulse counting circuit (COU2) 14 both use the clock pulse CLK.
, The count value is sequentially changed, but in the opposite direction. If one increases the count, the other decreases the count. Therefore,
The difference between the pulse number of the clock pulse CLK and the word length of the serial data S during the period when the word signal LR has a certain logical value is a second clock pulse counting circuit (COU2).
As a result, the shift operation of the parallel / serial conversion circuit (P / S) 12 is performed so that all the bits of the serial data S fall exactly between two adjacent significant edges of the word signal LR. Be started. That is, the transfer timing of the serial data S during the period in which the word signal LR takes the second logical value using the number of clock pulses CLK during the period in which the word signal LR takes the first logical value. Is controlled, and conversely, the serial data in the period in which the word signal LR takes the first logical value is utilized using the number of clock pulses CLK in the period in which the word signal LR takes the second logical value. The transfer timing of S is controlled.

Further, according to the first aspect of the present invention, a signal (edge detection signal a) for loading the parallel data P into the parallel / serial conversion circuit (P / S) 12.
Is generated by the edge detection circuit 11 based on the given word signal LR, so that the phase of the word signal LR does not change according to the position of the load signal LD unlike the related art. In addition, since all bits of the serial data S can be distributed so as to be exactly between two adjacent significant edges of the given word signal LR, the word signal L is determined according to the word length of the serial data S.
The phase of R does not change. Clock pulse CLK
The frequency ratio and the phase relationship between the word signal LR and the word signal LR are determined in advance, and the frequency ratio and the phase relationship do not change according to the word length of the serial data S or the like.

According to the invention of claim 2, according to claim 1,
As in the case of the invention, the start of the shift operation of the parallel-serial conversion circuit is waited. In addition, a storage circuit for selectively storing the count value of the first clock pulse counting circuit in accordance with the logical value of the word signal LR is provided between the first clock pulse counting circuit and the second clock pulse counting circuit. And the count initial value B1 of the second clock pulse counting circuit.
Is selected according to the logical value of the word signal LR,
The transfer timing of the serial data S during the next period when the word signal LR takes the first logical value is controlled using the number of clock pulses CLK during the period when the word signal LR takes the first logical value, The transfer timing of the serial data S during the next period when the word signal LR has the second logical value is controlled by using the number of clock pulses CLK during the period when the word signal LR has the second logical value. .
As a result, the number of clock pulses CLK during the period when the word signal LR has the first logical value matches the number of clock pulses CLK during the period when the word signal LR has the second logical value. Even when not performed, the transfer timing of the serial data S can be accurately controlled.

According to the third aspect of the present invention, as shown in FIG. 2, the first clock pulse counting circuit (COU1)
Reference numeral 13 denotes a negative initial value (for example, "-4") obtained by expressing a binary representation value of the number of bits (for example, 4 bits) per word of the serial data S to be transferred in two's complement, as the initial count value B1.
After that, the count value is sequentially increased in synchronization with the clock pulse CLK. On the other hand, the second clock pulse counting circuit (COU2) 14 outputs the first clock pulse counting circuit (COU2) at the time when the edge detection signal a is given.
1) After the count value (for example, “3”) of 13 before the initial setting is set as the count initial value B2, the clock pulse CL
K, the first clock pulse counting circuit (COU
1) Contrary to 13, the count value is sequentially reduced. These first
And second clock pulse counting circuit (COU1, 2) 1
In response to the counting operations of 3 and 14, the parallel / serial conversion circuit (P / S) 12 waits for the count value of the second clock pulse counting circuit (COU2) 14 to become negative, Start bit shift. In other words, the shift operation of the parallel / serial conversion circuit (P / S) 12 is started so that the serial data S to be transferred falls exactly between two adjacent significant edges of the word signal LR.

According to the fourth aspect of the present invention, the first clock pulse counting circuit (COU1) 13 controls the number of bits per word of the serial data S to be transferred (for example, 4 bits).
After the binary representation value (for example, “4”) of the bit pulse) is set as the positive count initial value B1, the clock pulse CL
The count value is sequentially reduced in synchronization with K. On the other hand, the second clock pulse counting circuit (COU2) 14 counts the count value (for example, “−”) of the first clock pulse counting circuit (COU1) 13 before the initial setting at the time when the edge detection signal a is given.
After 3 ″) is set as the count initial value B2, the count value is sequentially increased in synchronization with the clock pulse CLK, contrary to the first clock pulse counting circuit (COU1) 13. These first and second values are set. Clock pulse counting circuit (C
In response to the counting operations of OU1, 2) 13 and 14, the parallel / serial conversion circuit (P / S) 12 waits until the count value of the second clock pulse counting circuit (COU2) 14 becomes positive, The bit shift of the parallel data P is started. In other words, as in the case of the third aspect of the present invention, the shift of the parallel / serial conversion circuit (P / S) 12 is performed so that the serial data S to be transferred falls exactly between two adjacent significant edges of the word signal LR. The operation is started.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the serial data transfer device of the present invention. In FIG.
Is a word signal L supplied through the control signal input terminal 1.
An edge detection circuit for detecting both a rising edge and a falling edge of R and outputting a pulse-like edge detection signal a.
Parallel-serial conversion circuit (P /
S) and 13 are clock pulses C using B1 as the initial count value.
A first clock pulse counting circuit (COU1) for up-counting LK is used to count down the clock pulse CLK using the count value of the first clock pulse counting circuit (COU1) 13 as a count initial value B2. A second clock pulse counting circuit (COU2). The edge detection signal a output from the edge detection circuit 11 is
A parallel / serial conversion circuit (P / S) 12 and first and second clock pulse counting circuits (COU1, COU)
2) Applied commonly to the three components 13 and 14. Clock pulse CL applied through clock pulse input terminal 2
K is also commonly applied to these three blocks 12-14. The shift permission signal b is output from the second clock pulse counting circuit (COU2) 14 and supplied to the parallel / serial conversion circuit (P / S) 12.
The serial data S generated by bit-shifting the parallel data P by the parallel / serial conversion circuit (P / S) 12 is output through the serial data output terminal 3.

The operation of the serial data transfer apparatus according to the present embodiment having the above configuration will be described with reference to the timing chart shown in FIG. FIG. 2 shows a case where the number of bits per word of the serial data S to be transferred, that is, the word length is 4 bits, and the clock pulse CLK within one cycle of the word signal LR.
This is a description of a specific example of the operation when the number of pulses is 16. However, the number of clock pulses CLK during the period when the word signal LR has the first logical value “0” and the number of clock pulses CLK during the period when the word signal LR has the second logical value “1” Is 8 in all cases.

First, the operation of the first clock pulse counting circuit (COU1) 13 during the period in which the logical value of the word signal LR is "0" will be described for convenience of explanation. When the falling edge of the word signal LR arrives at the edge detection circuit 11 and the edge detection signal a is output from the edge detection circuit 11, the first clock pulse counting circuit (COU)
1) In 13, a negative value “−4”, which is a binary representation of the number of bits per word of the serial data S to be transferred and is represented by a two's complement, is set as a count initial value B1 (B1 =
-4). Thereafter, the first clock pulse counting circuit (COU
1) 13 counts up the clock pulse CLK. When the rising edge of the word signal LR arrives at the edge detection circuit 11 and the next edge detection signal a is output from the edge detection circuit 11, the count of the first clock pulse counting circuit (COU1) 13 is counted. The numerical value is “3”.

When the edge detection signal a corresponding to the rising edge of the word signal LR is output from the edge detection circuit 11 in this manner, the first clock pulse counting circuit (C
“OU1” 13 is set again with “−4” as the count initial value B1. At the same time, the count value “3” before the initial setting of the first clock pulse counting circuit (COU1) 13 at that time is set in the second clock pulse counting circuit (COU2) 14 as the count initial value B2. You. Further, parallel data P is loaded into the parallel / serial conversion circuit (P / S) 12, and BIT3 is output as the first bit of the serial data S.

Thereafter, the first clock pulse counting circuit (C
The OU1) 13 similarly counts up the clock pulse CLK, while the second clock pulse counting circuit (COU2) 14 counts down the clock pulse CLK. During this time, while the count value of the second clock pulse counting circuit (COU2) 14 is positive or 0, the shift permission signal b is "0" (shift is prohibited), and the second clock pulse counting circuit (COU2) When the count value of 14 becomes negative, the shift permission signal b becomes "1" (shift permission). The parallel / serial conversion circuit (P / S) 12 does not start bit shifting the loaded parallel data P while the shift permission signal b is “0”. The output serial data S holds BIT3. When the shift permission signal b becomes "1", the parallel / serial conversion circuit (P / S) 12 starts an operation of shifting the parallel data P one bit at a time in synchronization with the clock pulse CLK. The results are sequentially output as serial data S. As a result, the four bits of BIT3 to BIT0 are transferred as serial data S so as to fit exactly between the rising edge and the falling edge of the word signal LR.

As described above, using the number of clock pulses CLK during the period when the word signal LR takes the first logical value "0", the word signal LR is subsequently changed to the second logical value "0". The transfer timing of the serial data S during the period of “1” is controlled. Conversely, the word signal LR takes the first logical value "0" using the number of clock pulses CLK during the period in which the word signal LR takes the second logical value "1". The transfer timing of the serial data S during the period is controlled.

The edge detection circuit 11 outputs the word signal L
When adopting a configuration in which only the rising edge of R is detected as a significant edge indicating the timing of a break of one word of the serial data S to be transferred, or only the falling edge of the word signal LR is detected as a significant edge Also,
As described above, while keeping the frequency ratio and the phase relationship between the clock pulse CLK and the word signal LR constant, all bits of the serial data S just fall between two adjacent significant edges of the word signal LR. Thus, the serial data S can be sequentially transferred in synchronization with the clock pulse CLK.

The first clock pulse counting circuit (C
OU1) 13 has a binary expression value of the number of bits per word of serial data S to be transferred (4 in the above specific example).
"4" for the bit may be set as the positive count initial value B1. However, in this case, the first clock pulse counting circuit (COU1) 13 is a down counter,
The second clock pulse counting circuit (COU2) 14 is an up counter. The parallel-serial conversion circuit (P / S) 12 is provided with a second clock pulse counting circuit (CO
U2) It is assumed that it has a function of starting the bit shift of the parallel data P after the count value of 14 becomes positive.

Further, the number of clock pulses CLK during the period when the word signal LR has the first logical value "0" and the number of clock pulses during the period when the word signal LR has the second logical value "1" In order to cope with the case where the number of pulses of the pulse CLK does not match, the count value of the first clock pulse counting circuit (COU1) 13 is set to the word signal L.
The first clock pulse counting circuit (COU1) 13 and the second clock pulse counting circuit (COU1)
, And an initial count value B1 of the second clock pulse counting circuit (COU2) 14 is selected from the storage circuit according to the logical value of the word signal LR. At this time, the word signal LR becomes the first
Of the clock pulse CL during the period in which the logical value “0” is taken
Using the number of pulses of K, the transfer timing of the serial data S during the period when the word signal LR takes the first logical value “0” next is controlled, and the word signal LR becomes the second logical value “1”.
Is used to control the transfer timing of the serial data S during the period when the word signal LR takes the second logical value “1” using the pulse number of the clock pulse CLK during the period during which the serial data S The transfer timing is accurately controlled.

[0032]

As described above, according to the first aspect of the present invention, a two-stage clock pulse counting circuit (C) is provided based on a given word signal LR and clock pulse CLK.
OU1, COU2) 13 and 14 are controlled to determine the shift timing of the parallel / serial conversion circuit (P / S) 12, so that the frequency ratio between the clock pulse CLK and the word signal LR is reduced. While serially maintaining the phase relationship constant, the serial data S is sequentially transferred in synchronization with the clock pulse CLK so that all bits of the serial data S fall exactly between two adjacent significant edges of the word signal LR. A data transfer device can be realized and flexible serial data
A data transfer system can be constructed.

According to the second aspect of the present invention, the storage circuit for selectively storing the count value of the first clock pulse counting circuit in accordance with the logical value of the word signal LR is provided. A circuit is provided between the second clock pulse counting circuit and the second clock pulse counting circuit, and the initial count value B1 of the second clock pulse counting circuit is selected according to the logical value of the word signal LR. Even when the number of pulses of the clock pulse CLK during the period in which the logical value is 1 does not match the number of pulses of the clock pulse CLK in the period in which the word signal LR has the second logical value, the serial data S The transfer timing can be accurately controlled.

Further, according to the third aspect of the present invention, the first clock is defined as a count initial value B1 that is a negative value obtained by expressing a binary representation of the number of bits per word of the serial data S to be transferred in two's complement. Since the configuration in which the pulse count circuit (COU1) 13 is set is adopted, the count value of the first clock pulse count circuit (COU1) 13 is used as the count initial value B2. The parallel-serial conversion circuit (P /
S) The start of the shift operation of 12 can be controlled, and the circuit configuration can be simplified.

According to the fourth aspect of the present invention, the first clock pulse counting circuit (COU1) 13 sets the binary representation value of the number of bits per word of the serial data S to be transferred as the positive count initial value B1. The second clock pulse counting circuit (COU1) 13 uses the count value of the first clock pulse counting circuit (COU1) 13 as the count initial value B2 as in the case of the third aspect of the present invention. COU
2) The start of the shift operation of the parallel / serial conversion circuit (P / S) 12 can be controlled only by the sign of the count value of 14, and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a serial data transfer device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the serial data transfer device of FIG. 1;

FIG. 3 is a timing chart showing an example of transfer timing to be satisfied by a serial data transfer device.

FIG. 4 is a block diagram of a conventional serial data transfer device.

FIG. 5 is a timing chart for explaining the operation of the serial data transfer device of FIG. 4;

[Explanation of symbols]

 Reference Signs List 11 edge detection circuit 12 parallel / serial conversion circuit (P / S) 13 first clock pulse counting circuit (COU1) 14 second clock pulse counting circuit (COU2) a edge detection signal b shift enable signal B1 first clock pulse Counting initial value of counting circuit B2 Counting initial value of second clock pulse counting circuit CLK Clock pulse LR Word signal P Parallel data S Serial data

Claims (4)

(57) [Claims] 1. A word signal which is a binary logic signal and at least one of a rising edge and a falling edge is a significant edge indicating a timing of a break of one word of serial data to be transferred. An edge detection circuit that outputs an edge detection signal each time a significant edge of the word signal is supplied; and a bit per word of serial data to be transferred when the edge detection signal is supplied from the edge detection circuit. A first clock pulse for sequentially changing the count value in a predetermined direction in synchronization with the clock pulse until a value indicating a number is set as a count initial value and the next time an edge detection signal is given from the edge detection circuit A counting circuit, and when the edge detection signal from the edge detection circuit is given, the first clock pulse at that time. The count value before the initial setting of the several circuits is set as a count initial value, and the first clock pulse counting circuit and the first clock pulse counting circuit are synchronized with the clock pulse until the next time when the edge detection signal is supplied from the edge detection circuit. A second clock pulse counting circuit for sequentially changing the count value in the opposite direction, and when the edge detection signal from the edge detection circuit is given, parallel data to be converted into serial data is loaded, and Until the edge detection signal is supplied from the edge detection circuit, a bit shift of the loaded parallel data synchronized with the clock pulse is started under the control of the count value of the second clock pulse counting circuit, A serial-to-serial conversion circuit for sequentially outputting the result of the bit shift as serial data. Rudeta transfer device. 2. A word signal, which is a binary logic signal, in which both a rising edge and a falling edge are significant edges indicating a timing of a break of one word of serial data to be transferred, and the word signal is provided. An edge detection circuit that outputs an edge detection signal each time a significant edge is given, and a value indicating the number of bits per word of serial data to be transferred when the edge detection signal is given from the edge detection circuit. A first clock pulse counting circuit that is set as a count initial value, and sequentially changes a count value in a predetermined direction in synchronization with a clock pulse until a time point when an edge detection signal is next supplied from the edge detection circuit; From the time when an edge detection signal corresponding to the rising edge of the word signal is supplied from the edge detection circuit, the first While the count value before the initialization of the lock pulse counting circuit is held as a first storage value, the first detection value at the time from the time when the edge detection signal corresponding to the falling edge of the word signal is given. A storage circuit for holding a count value before initialization of the clock pulse counting circuit as a second storage value separately from the first storage value; and detecting an edge corresponding to a rising edge of the word signal from the edge detection circuit. At the time when the signal is applied, the second storage value of the storage circuit is set as the count initial value, while at the time when the edge detection signal corresponding to the falling edge of the word signal is applied, the second storage value of the storage circuit is set. The first stored value of the storage circuit is set as the initial count value in place of the stored value of 2, and until each time any of the edge detection signals is supplied from the edge detection circuit, each of the total values is counted. A second clock pulse counting circuit for sequentially changing a count value in a direction opposite to the first clock pulse counting circuit in synchronization with the clock pulse based on the initial value; and an edge detection signal from the edge detection circuit. Is supplied, parallel data to be converted to serial data is loaded, and until the next time when the edge detection signal is supplied from the edge detection circuit, control is performed under the control of the count value of the second clock pulse counting circuit. And a parallel-to-serial conversion circuit for starting a bit shift of the loaded parallel data in synchronization with the clock pulse and sequentially outputting a result of the bit shift as serial data. 3. The serial data transfer device according to claim 1, wherein said first clock pulse counting circuit is a two's complement representation of a binary representation value of the number of bits per word of the serial data to be transmitted. A function of sequentially increasing the count value in synchronization with the clock pulse after the set negative value is set as a count initial value, wherein the second clock pulse counting circuit sequentially counts the count value in synchronization with the clock pulse. The serial-to-serial conversion circuit has a function of starting a bit shift of the parallel data after the count value of the second clock pulse counting circuit becomes negative. Data transfer device. 4. The serial data transfer device according to claim 1, wherein said first clock pulse counting circuit has a positive initial value in a binary representation value of the number of bits per word of serial data to be transferred. A function of sequentially decreasing the count value in synchronization with the clock pulse after being set as a value; a function of sequentially increasing the count value in synchronization with the clock pulse; A serial data transfer device, wherein each of the serial conversion circuits has a function of starting a bit shift of the parallel data after the count value of the second clock pulse counting circuit becomes positive.