JPH11308296A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer many data at a high speed efficiently with a simple configuration with respect to the data transfer system. SOLUTION: A data transmission section 20 sequentially compares transmission data with pattern data and transfers the transmission data to 1st signal line serially while giving a 1-bit length to a 1st signal level when matching and giving a prescribed bit length to a 2nd signal level when nonmatching and transfers the nonmatching transmission data serially to the 2nd signal line synchronously with the 2nd signal level. A data reception section 50 decodes received data corresponding to the 1st signal level of the 1st signal line with pattern data and decodes the received data corresponding to the 2nd signal level with the received serial data of the 2nd signal line. Or header data representing matching/nonmatching of comparison are serially transferred at first and succeedingly only nonmatching transmission data are transferred serially.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system, and is suitable for application to information communication between a control package and a controlled package within a device or between devices. Today, for example, in a data transmission device, with the high performance and high functionality of a controlled package that performs various main signal processing, control data and monitoring data exchanged with a control package that controls and monitors these packages have been increasing. The demand has been greatly increased, which requires faster and more efficient data transfer.

[0002]

2. Description of the Related Art FIG. 12 is a diagram for explaining a conventional technique, and shows a configuration of a data transfer system. In the figure, 10
0 ₁ , 100 ₂ is a data transmission device having a rack structure accommodating a large number of packages, 1 is a plurality of controlled packages 4
₁ to 4 _n, etc. to the control data control package for collecting and managing the monitoring data from the controlled package 4 ₁ to 4 _n, etc. and transmits the (parameter setting data), 2 data transfer control unit (usually an LSI 3 is a memory for storing control data and monitoring data, and 4 ₁ to 4 _n are responsible for various main signal processing in the data transmission device 100 under the control of the control package 1 and for collecting and transferring monitoring data. The control package 5 has a data transfer control unit (L
SI) and 6 are memories for storing control data and monitoring data, 7 is a signal connection line between packages inside the device, and 8 is a signal connection cable between packages outside the device.

[0003] With such a configuration, conventionally, the package 1,
The control data and monitoring data exchanged between 4 (or 1, 1) are directly converted into serial data of a predetermined format and serially transferred.

[0004]

However, with the large increase in the amount of data communication of this type in recent years, there is a limit to data transfer within a required time (real time). SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the related art, and has as its object to provide a data transfer method capable of transferring a large amount of data at high speed and efficiently with a simple configuration.

[0005]

The above-mentioned problem is solved, for example, by referring to FIG.
The problem is solved by the configuration of (A). That is, the data transfer method of the present invention (1) uses the data transmission unit 20 for transmitting data.
In a data transfer method for transferring data between the data transmitting unit 2 and the data receiving unit 50 for receiving the data, the data transmitting unit 2
0 indicates that the transmission data TD having the predetermined number of bits is sequentially compared with the pattern data PD having the predetermined number of bits, and if the match is obtained, the first signal level has a 1-bit length and does not match. Is transmitted serially to the first signal line with the predetermined bit length, and the transmission data B ₁ ,
The B ₆ to the second signal line in synchronization with the second signal level is to serial transfer.

In this case, by setting a data pattern which is most frequently transferred as the pattern data PD, a high data compression rate and a short transfer time can be obtained. Preferably, in the present invention (2), in the above-mentioned present invention (1), the data receiving section 50 receives the reception data RD corresponding to the first signal level received via the first signal line.
Is restored by pattern data PD having a predetermined number of bits, and received data RD corresponding to the second signal level is restored by serial data (unmatched data) B ₁ and B ₆ received via the second signal line. I do.

The above-mentioned problem is solved, for example, by the structure shown in FIG. That is, in the data transfer method of the present invention (3), in the data transfer method of transferring data between the data transmitting unit 20 for transmitting data and the data receiving unit 50 for receiving the data, A predetermined number of pieces of transmission data TD having a predetermined number of bits are sequentially compared with the pattern data PD having the predetermined number of bits, and header data having the predetermined number of bits representing a match / mismatch therebetween is generated. In addition to the serial transmission to the signal line, only the transmission data B ₁ and B _{6 in} the case of the non-coincidence are serially transmitted to the signal line.

In the present invention (3), since only one signal line is required, wiring can be easily performed. Preferably, in the present invention (4), in the above present invention (3), the data receiving section 50 sequentially checks the signal level of the header data received via the signal line in a bit-by-bit manner, In the case of the first signal level indicating the comparison match, the corresponding received data RD is restored by the pattern data PD having a predetermined number of bits, and the second signal indicating the comparison mismatch is restored.
In the case of the signal level of, the serial data B ₁ and B ₆ received after the header data are sequentially restored.

Preferably, in the present invention (5), in the above-mentioned present invention (1) or (3), the data transmitting section 20 comprises a predetermined number of pattern data PD (P ₀₎ consisting of an integral multiple of a predetermined number of bits. To P ₇ ), and each transmission data T
D and the predetermined number of each pattern data PD are sequentially compared. More preferably, in the present invention (6), in the present invention (2) or (4), the data receiving unit 50
A predetermined number of pattern data PD (P _{0 to} P ₇ ) which is an integral multiple of a predetermined number of bits is provided, and each received data RD corresponding to each received first signal level is converted into the predetermined number of pattern data P ₀ to P ₀ . to restore the corresponding pattern data of the P _7.

Preferably, in the present invention (7), in the present invention (5), the data transmitting unit 20
This predetermined number of transmission data TD replaces the predetermined number of pattern data PD for the next processing. For example, if the pattern data PD of one P ₀ is replaced each time the pattern data P ₀ by the transmission data B ₀ ~B _7. In the case the pattern data PD of eight P ₀ to P ₇ sequentially replacing the pattern data P ₀ to P ₇ for each corresponding the transmission data B ₀ ~B _7.

Therefore, the next time, only the transmission data whose bits have changed need to be serially transferred, and a high data compression rate and a short transfer time can be obtained. Also preferably, in the present invention (8), in the present invention (6), the data receiving unit 50 uses the predetermined number of received data RD this time to transmit the predetermined number of pattern data P for the next processing.
Replace D.

[0012]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing the configuration of the data transfer system according to the first embodiment, in which a data transmission / reception unit is connected by two signal lines and a comparison result of comparing transmission data with pattern data And the serial transfer of the comparison data and the transmission data (compressed data) of only the comparison mismatch are synchronized.

In FIG. 1, reference numeral 20 denotes a transmission memory (not shown).
A data compression transmission unit 50 for compressing the parallel transmission data from the data and serially transmitting the data, a data reception unit 50 for converting the received serial data into parallel data, restoring the data of the data compressed part, and outputting the data to a reception memory (not shown) It is an extension part. In the data compression transmission unit 20, P / S
Is a parallel-serial conversion unit that converts the parallel transmission data TD0 to TD7 into serial data, RG1 is a register holding pattern data PD0 to PD7 for one byte, CMP is a comparator that compares the transmission data TD with the pattern data PD, A1 is an AND gate circuit that performs P / S shift control according to the comparison result of CMP, and CT1.
Is a 3-bit counter that counts the number of P / S bit shifts, and T1 and T2 are drivers that transmit serial data.

Here, the P / S operates in synchronization with the fall of the clock signal CK, and when the shift enable signal SE1 = 0 (LOW level), the input transmission data T
D0 to TD7 are loaded, and SE1 = 1 (HIGH
When the level) its retained data is one bit shifted from the bit b ₇ to the direction of the bit b _0. In the data reception decompression unit 50, R1 and R2 are receivers for receiving serial data, S / P is a serial-parallel conversion unit for converting received serial data to received parallel data,
T2 is a 3-bit counter for counting the number of S / P bit shifts, and RG2 is 1-byte pattern data PD.
0 to PD7, SEL is a selector for selecting received parallel data or pattern data PD, F
F is a D-type flip-flop that generates the SEL selection signal SL, and NO is a NOR gate circuit.

Here, the S / P operates in synchronization with the fall of the clock signal CK, and does not shift in the input received serial data when the shift enable signal SE2 = 0 (LOW level). SE2 = 1 with time (HIGH-level) to shift in the received serial data input on the side of the bit b _7, shift out data bits b _0.

FIG. 3 is a timing chart of the data transfer method according to the first embodiment. Hereinafter, the circuit operation will be described in detail with reference to FIGS. Here, RG1, R
Together, for example, "00000000" each pattern data PD0~PD7 of G2, and describes a case of transferring eight bytes transmitted B ₀ .about.B ₇ in total.

When the first transmission byte B ₀ = “000000000” is input to the data compression transmission unit 20, T
Due to D = PD, CMP mismatch detection signal A ≠ B = 0 (L
OW level). Accordingly, at the first transmission bit timing, comparison data = bit 0 (indicating compression) is transmitted from the driver T1, and the next transmission byte B ₁ = “01101110” is P / S at the falling edge of the clock signal CK.
Is loaded.

This time, due to TD ≠ PD, the CMP mismatch detection signal A ≠ B = 1 (HIGH level). on the other hand,
Since the count output of CT1 = “0”, the AND gate circuit A1 is satisfied, and the P / S enters the shift mode. As a result, the transmission byte B ₁ is shifted out sequentially from the bit b ₀ side. Therefore, at the next eight transmission bit timings, the comparison data = bit 1 (representing uncompressed) is transmitted from the driver T1, and at the same time, uncompressed data = “01101110” is transmitted from the driver T2 as compressed data.

At this time, CT1 outputs the clock signal C
Count up with K, then count output =
When it becomes "7", the carry signal C becomes 1, and the AND gate circuit A1 is deactivated. This shift mode P / S is de-energized, the new transmission byte B ₂ is at the falling edge of the next clock signal CK is loaded. For subsequent a respective transmit byte B ₂ .about.B ₅ = "00000000", comparison data = bit 0 from the driver T1 in the same manner as described above
(Compression) is transmitted, and at the same time, for example, compressed data = bit 0 is transmitted from the driver T2. The signal level of the compressed data in the period of comparison data = bit 0 is
Since the content of the compressed data is known on the receiving side, any signal level may be used.

Next, the transmission byte B ₆ = “1010001”
When "1" is input, the CMP mismatch detection signal A ≠ B = 1
In the same manner as above, the comparison data = bit 1 is transmitted from the driver T1 at the subsequent eight transmission bit timings, and at the same time, uncompressed data = “101000011” is transmitted from the driver T2 as compressed data. Since the last transmission byte B ₇ = “00000000”, the comparison data = bit 0 from the driver T1.
However, compressed data = bit 0 is transmitted from the driver T2.

On the other hand, when the first comparison data = bit 0 is input from the receiver R1 in the data reception decompression unit 50, the SEL selects the pattern data PD of RG2 by the selection signal SL = 0, and the output reception byte B ₀ = "0
00000000 ". Next, when comparison data = bit 1 is input, the shift enable signal SE2 =
1 sets the shift mode. This allows the receiver R2
If compressed data from is shifted in the order from the side of the bit b ₇ of S / P, eventually elapses 8 clocks, S /
P stores parallel data = “01101110”.

At this time, CT2 counts up by the clock signal CK, and the count output = "1" to "7"
, The NOR gate circuit NO is activated, and the data write inhibit signal WDS to the external memory (not shown) is activated. When the count output = “7”, the carry signal C = 1, thereby setting the output Q of the FF (that is, the selection signal SL) to “1” for the next one clock period. As a result, the S / P parallel data is selected in the SEL,
The output reception byte B ₁ = “01101110”.
At this timing, the input comparison data = bit 0, whereby both the S / P shift mode SE2 and the CT2 count mode CE are deactivated.

In the subsequent four clock periods, since the input comparison data = bit 0, the pattern data PD of RG2 is continuously selected by the SEL in the same manner as described above, and the output reception bytes B _{2 to} B ₅ = "00000000". Next, when the input comparison data = bit 1, the output received byte B ₆ = “10100011” in the same manner as described above.
Becomes Then, since the last comparison data = bit 0, the output received byte B ₇ = “00000000”.

The pattern data PD can be arbitrarily set in advance by the system. Preferably, by setting a data pattern which is statistically most frequently transferred, a high data compression ratio and a short transfer time can be obtained. In the case where a plurality of bytes of block data are burst-transferred between data transmission / reception units, a synchronization bit signal or a synchronization byte signal for obtaining frame synchronization is transmitted to a signal line of comparison data or compressed data. Then, synchronization may be obtained on the receiving side.

FIG. 4 is a diagram showing a configuration of a data transfer system according to the second embodiment. A data transmission / reception unit is connected by one signal line, and data of a comparison result (that is, coincidence) is first obtained. / Pattern data of non-matching) and then serially transferring only transmission data of non-matching. In the data compression transmission unit 20, DPRAM1 is a dual-port memory (buffer memory) for temporarily storing only transmission data that does not match, CM1 is a comparator for comparing input transmission data TD with pattern data PD of RG1, and WC1 is a comparator. DP
A write counter for generating a data write address WA of the RAM 1, RC 1 is a data read address RA of the DPRAM 1
, A comparator for comparing the data write address WA of the DPRAM1 with the data read address RA, and a SQC1 for controlling the sequence of data compression transmission.

In the data receiving / expanding section 50, the DPRA
M2 is a dual port memory (buffer memory) for temporarily storing serial-to-parallel converted received data (mismatch data), WC2 is a write counter for generating a data write address WA of the DPRAM2, and RC2 is a DP.
A read counter for generating a data read address RA of the RAM 2, and CM 3 is a data write address WA of the DPRAM 2
And a comparator for comparing the data read address RA with
SQC2 is a sequence control unit that performs sequence control of data reception expansion.

FIGS. 5 and 6 are timing charts (1) and (2) of the data transfer method according to the second embodiment. The circuit operation will be described in detail below with reference to FIGS.
In FIG. 5, for example, eight transmission bytes B _{0 to} B ₇ are continuously input to the data compression transmission unit 20. At this time, the comparator CM1 compares each of the transmission bytes B _{0 to} B ₇ with the pattern byte P _0, and when they match, the mismatch detection signal A ≠ B = 0, and when they do not match, the mismatch detection signal A
≠ B = 1 is output. P / S is the mismatch detection signal A ≠
By sequentially shifting in respective signal levels from the side of the bit b ₇ of B, the comparison result at the time the eight bytes transmitted B ₀ .about.B ₇ input is compared pattern data = "0100
0010 ”.

The mismatch detection signal A 信号 B is a DPR
AM1 write enable terminal WE and write counter WC1
, The DPRAM 1 stores only the transmission bytes that do not match, and WC1 is incremented by +1 after writing each transmission byte.
In this example, only the two transmission bytes B ₁ and B ₆ do not match, the transmission byte B ₁ is written at the address 0 of the DPRAM ₁ and the transmission byte B ₆ is written at the address 1 and the count output of the WC 1 is finally It is "2".

When the input cycle of the transmission bytes B _{0 to} B ₇ ends, the SQC 1 starts a transmission cycle of the compressed data. Initially, only the P / S is operated, and the pattern data (also referred to as header data) of the comparison result stored in the P / S = “01000010” is stored in the bit b _0.
Shift out sequentially from the side. Next, 0 of DPRAM1
The transmission byte B ₁ = “01101110” is read from the address and set to P / S, and this is sequentially shifted out from the bit b ₀ side. Next, the transmission byte B ₆ = “101000011” is read from address 1 of the DPRAM 1 and P /
Set to S, sequentially shifts out this from the side of the bit b _0.

On the other hand, at this time, the comparator CM2 has detected WA = RA, and therefore no further data reading from the DPRAM1 is performed. That is, the end of serial transmission of the compressed data with a transmission of the transmission byte B _6. In FIG. 6, the compressed data transmitted serially is input to the data receiving / expanding section 50. S / P is bit b
_{When the} input serial compressed data is shifted in from the side _{7 and} the data of 8 bits is accumulated, the bit full signal F is set to "1" for one bit section.

SQC2 is the first bit full signal F = 1
Starts a cycle of counting the number of bits of “1” in the received header byte (ie, the number of mismatched bytes). The reading counter RC2 is used for this counting. Specifically, S / the second interval serial compressed data B ₁ is being shifted in the P, the bit b of the header data = "01000010" is the S / P accumulated in the S / P Shifted out sequentially from the ₀ side. The SQC2 calculates the header data = “0100001”
"0" is stored therein, and the bit = "1" of the header data in this section is monitored. When the bit = "1" is detected, +1 is added to RC2 each time. Thus, in this example, the count output of RC2 finally becomes "2". Since this section is not a restoration cycle of the reception data RD, unnecessary data is not taken into the system.

Further, SQC2 by the detection of the second bit full signal F = 1, writes the received compressed byte B ₁ stored in the S / P at that time address 0 of the DPRAM 2, thereafter WC2 +1 I do. Furthermore, SQC2
Detects the third bit full signal F = 1, and writes the received compressed byte B ₆ stored in the S / P at the address 1 in the DPRAM 2 at that time, and then writes WC 2
+1.

At this time, the count output of WC2 is "2", whereby CM3 detects RA = WA and informs SQC2 of that. As a result, the SQC 2 ends the serial compressed data reception cycle, and subsequently starts the decompression cycle of the received data RD. The restoration of the reception data RD is performed using the pattern of the header data = "01000010" stored inside the SQC2.

Specifically, first, the read counter RC2
Clear Next, bit b of the header data₀See
And the b₀= “0” means that SEL of RG2
Select pattern data PD, and₀= "0
00000000 "is output. Next, the bit of the header data
B₁With reference to b₁= "1" means SE
Read byte B at address 0 of DPRAM2 in L₁Selected
And receive byte B₁= Output "01101110"
You. At this time, +1 is added to RC2. Each header data
B_Two~ B_Five= "0" and the same as above
Receive byte B_Two~ B _Five= Output "00000000"
I do. Next, bit b of the header data₆With reference to b₆
= 1 for DPRAM2 in SEL due to “1”
Read byte B of the ground₆And select the received byte B₆= "1
00010001 "is output. At this time, +1 is added to RC2
You. Next, bit b of the header data₇= "0"
By receiving byte B₇= Output "00000000"
You.

Then, the SQC 2 ends the restoration cycle of the received data by ending the restoration processing of the bit b ₇ of the header data. FIG. 7 is a diagram showing a configuration of a data transfer method according to the third embodiment. The data transfer method is basically the same as the data transfer method according to the first embodiment, but is the same as a transmission data block consisting of a plurality of bytes. A case where data comparison with a pattern data block consisting of a plurality of bytes is performed is shown.

In the figure, RAM1 and RAM2 are random access memories each storing a pattern data block composed of a plurality of bytes, and RWC1 and RWC2 are each an R memory.
AM1, RAM2 data reading control unit, O1, O2 is O
An R gate circuit (consisting of a plurality). Other configurations may be the same as those described with reference to FIG. RAM
1, RAM2, for example, eight pattern bytes P
₀ ~P ₇ is stored. These are used as input transmission bytes B _0.
If you are also shown along with the ~B _7, is in as follows, B ₀ = "10000000" * P ₀ = "00000000" * B ₁ = "01101110" P ₁ = "01101110" B ₂ = "11000000" * P ₂ = " 00000000 * B ₃ = “00000000” P ₃ = “00000000” B ₄ = “00000000” P ₄ = “00000000” B ₅ = “00000000” P ₅ = “00000000” B ₆ = “101000011” P ₆ = “101000011” B ₇ = “00000000” P ₇ = “00000000” Here, the transmission bytes B ₀ and B ₂ and the pattern bytes P ₀ and
P ₂ is different from each other.

FIG. 8 is a timing chart of the data transfer method according to the third embodiment. Data compression transmission unit 2
At 0, the data reading control unit RWC1 is energized the data read control by the timing signal TS1 from the system, each from RAM1 each transmit byte B ₀ .about.B ₇ in synchronism with the timing for loading the P / S It reads the pattern bytes P ₀ ~P ₇ in the order. CMP compares the transmission byte B ₀ .about.B ₇ input patterns byte P ₀ to P ₇ in order to output a corresponding mismatch detection signal A ≠ B = 0/1. Subsequent operations can be considered in the same manner as described with reference to FIG.

In the data receiving / expanding section 50, the data reading control section RWC2 receives a timing signal TS from the system.
While being urged the data read control by 2, R in synchronization with the timing of restoring each received byte B ₀ .about.B ₇
Reading each pattern byte P ₀ ~P ₇ in the order from the AM2. However, in this example, S / P parallel conversion output is selected for the received bytes B ₀ and B ₂ .

The third embodiment is suitable for application to periodic data transfer of block monitor bytes B _{0 to} B ₇ in a data transmission device or the like. That generally block monitoring byte B ₀ .about.B ₇ of this kind has a specific bit pattern different for each byte, and looking at it in a short time, only a certain few bits of these changes It is considered something. Therefore, since only one or more mismatched bytes including a change bit can be transferred in an uncompressed state, and most other bytes can be transferred in a compressed state, a block having a complicated bit pattern as a whole can be transferred. Even in the data transfer of the monitoring byte, a high data compression rate and high-speed transfer can be expected.

Now, returning to FIG. 7, the third embodiment will be described.
The data compression transmission unit 20 according to
Each pattern byte P of the RAM 1 is output via the scanning circuit O1.₀
~ P ₇Input each transmission byte B₀~ B₇Rewritable by
It has become. This rewrite is based on the current transmission byte and the current
Performed after comparison with the pattern byte. Also, this rewrite
Pattern by which a mismatch was found with the transmitted byte of force
May be rewritten only, or all patterns are unconditionally
Byte P₀~ P₇Is the input transmission byte B₀~ B₇To
It may be rewritten more. In any case, R at the next point in time
AM1 is always the previous transmission byte B₀~ B₇Remember
And As a result, the CMP in this case is
By comparing the block and this transmission block
Only unmatched bytes containing different bits are uncompressed
It will be transferred in state.

On the other hand, also in the data receiving / expanding section 50, each pattern byte P
It has become rewritable to ₀ to P ₇ by the received byte B ₀ .about.B ₇ outputs. This rewriting is performed after the currently received byte is restored. Also this rewriting, to only the pattern byte when RAM2 output is not selected may be rewritten in the corresponding received byte, or receiving the output of all of the pattern byte P ₀ to P ₇ unconditionally byte B ₀ it may be rewritten by ~B _7. In any case, the RAM 2 at the next point in time
Always it will store the received byte B ₀ .about.B ₇ last. As a result, in this case, the SEL selects and outputs only the non-coincidence byte at this time from the S / P side, and each other reception byte is provided by the previous reception byte of the RAM 2.

Thus, according to the third embodiment, the present transmission data block is compared with the previous transmission data block (that is, the current pattern data block) and the current transmission data block. Only when a bit change occurs, the byte can be transferred in an uncompressed state, and in other sections, all bytes can be transferred in a compressed state. Therefore, a high data compression rate and high-speed transfer can be expected.

FIG. 9 is a diagram showing the configuration of a data transfer method according to the fourth embodiment. The data transfer method is basically the same as the data transfer method according to the second embodiment, except that transmission data consisting of a plurality of bytes is used. The figure shows a case where data comparison is performed between a block and a pattern data block composed of the same plural bytes. In the figure, RAM1 and RAM2 are random access memories each storing a pattern data block composed of a plurality of bytes, and O1 and O2 are OR gate circuits (composed of a plurality). Other configurations may be the same as those described with reference to FIG.

FIGS. 10 and 11 are timing charts (1) and (2) of the data transfer method according to the fourth embodiment. In FIG. 10, when, for example, eight transmission bytes B _{0 to} B ₇ are successively input to the data compression transmission unit 20, eight pattern bytes P _{0 to} P ₇ are sequentially transmitted from the RAM 1 in synchronization with the transmission bytes B _{0 to} B _7. Is read. The transmission mismatch bytes in this example are B ₀ and B ₂ . Subsequent operations can be considered in the same manner as described with reference to FIG.

In FIG. 11, the data receiving / expanding section 50
Is the received unmatched data B₀, B _TwoIs converted to parallel
Received byte B₀, B_TwoAnd the other receiving
It B₁, B_Three~ B₇Is each pattern byte P of RAM2
₁, P_Three~ P₇Provided by Therefore, the fourth actual
This embodiment is based on the block monitor
It B₀~ B₇Suitable for regular data transfer
is there.

Returning to FIG. 9, the data compressing and transmitting section 20 according to the fourth embodiment further transmits each of the pattern bytes P ₀ -P _{0 of the} RAM 1 via the OR gate circuit O 1.
P ₇ has a rewritable by each transmit byte B ₀ .about.B ₇ inputs a, thereby RAM1 will always be stored transmit byte B ₀ .about.B ₇ last. As a result, the CMP in this case compares the previous transmission block with the current transmission block and outputs a comparison non-coincidence signal A ≠ B = 1 only when a different bit is included, whereby the header data representing the non-coincidence byte is output. Then, only the uncompressed data of the mismatched byte is serially transferred.

On the other hand, in the data receiving / expanding section 50, each pattern byte P ₀ to
By each received byte B ₀ .about.B ₇ outputs the P ₇ it has a rewritable, thereby RAM2 is always to store the received byte B ₀ .about.B ₇ last. As a result, the SEL in this case uses only the received
Selective output from M2 side, other received bytes are R
It will be provided by each previous received byte of AM2.

Thus, according to the fourth embodiment, only when a bit change occurs in the current transmission data block, the mismatched byte is transferred in an uncompressed state, and in the other sections, the header byte is transferred. Since only the data needs to be transferred, a high data compression rate and high-speed transfer can be expected.
In each of the above embodiments, a one-way configuration for performing data transfer from the data compression / transmission unit 20 to the data reception / decompression unit 50 has been described. However, such a configuration can be provided bidirectionally between packages or devices. Bidirectional transfer (communication) of control data, monitoring data, and the like can be performed efficiently.

In each of the above embodiments, the processing is performed in units of bytes. However, it is needless to say that processing can be performed in units of any other number of bits. Further, a plurality of embodiments suitable for the present invention have been described, but the present invention is not limited to these embodiments. It is needless to say that the present invention can be realized by other various methods (other hardware configurations, software processing by a CPU or the like) without departing from the spirit of the present invention.

[0050]

As described above, according to the present invention, a large amount of data can be transferred at high speed and efficiently with a simple configuration, which greatly contributes to the improvement of the performance of data transfer within or between devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a configuration of a data transfer method according to the first embodiment.

FIG. 3 is a timing chart of a data transfer method according to the first embodiment.

FIG. 4 is a diagram showing a configuration of a data transfer method according to a second embodiment.

FIG. 5 is a timing chart (1) of a data transfer method according to the second embodiment.

FIG. 6 is a timing chart (2) of the data transfer method according to the second embodiment.

FIG. 7 is a diagram illustrating a configuration of a data transfer method according to a third embodiment.

FIG. 8 is a timing chart of a data transfer method according to the third embodiment.

FIG. 9 is a diagram showing a configuration of a data transfer method according to a fourth embodiment.

FIG. 10 is a timing chart (1) of a data transfer method according to a fourth embodiment.

FIG. 11 is a timing chart (2) of the data transfer method according to the fourth embodiment.

FIG. 12 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 Reference Signs List 20 data compression / transmission unit 50 data reception / decompression unit A AND gate circuit CMP (CM) comparator CT counter FF flip-flop NO NOR gate circuit O OR gate circuit P / S parallel-serial conversion unit R receiver RAM random access memory RC read counter RG Register RWC Reading control unit SEL selector SQC Sequence control unit S / P Serial-parallel conversion unit T driver WC write counter

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Koichi Kitamura 2-2-6 Jomi, Chuo-ku, Osaka-shi, Osaka Fujitsu Kansai Digital Technology Co., Ltd. In-house

Claims (8)

[Claims] 1. A data transfer method for transferring data between a data transmitting unit for transmitting data and a data receiving unit for receiving the data, the data transmitting unit comprising: a transmission data having a predetermined number of bits; The pattern data is sequentially compared with the pattern data consisting of the number of bits, and the first signal level when a match is obtained has a 1-bit length, and the second signal level when the match has not been obtained has a predetermined bit length. A data transfer method, wherein the data is serially transferred to one signal line, and the transmission data in the case of the mismatch is serially transferred to a second signal line in synchronization with the second signal level. 2. The data receiving section restores received data corresponding to a first signal level received via a first signal line using pattern data having a predetermined number of bits,
2. The data transfer method according to claim 1, wherein received data corresponding to the second signal level is restored by serial data received via the second signal line. 3. A data transfer system for transferring data between a data transmitting unit for transmitting data and a data receiving unit for receiving the data, wherein the data transmitting unit includes a predetermined number of transmission data bits each including a predetermined number of bits. And the pattern data consisting of the predetermined number of bits are sequentially compared to generate header data consisting of the predetermined number of bits representing the match / mismatch between them, and serially transferred to a signal line. A data transfer method, wherein only transmission data in the case is serially transferred to the signal line. 4. The data receiving section sequentially checks the signal level of the header data received via the signal line on a bit-by-bit basis, and when the signal level is a first signal level indicating a comparison match, the corresponding reception level is determined. 4. The method according to claim 3, wherein the data is restored by pattern data having a predetermined number of bits, and in the case of a second signal level indicating a comparison mismatch, the header data is sequentially restored by each received serial data. Data transfer method described. 5. A data transmission unit comprising a predetermined number of pattern data consisting of an integral multiple of a predetermined number of bits, and sequentially comparing each transmission data with the predetermined number of pattern data. Or the data transfer method according to 3. 6. A data receiving section comprising a predetermined number of pattern data consisting of an integral multiple of a predetermined number of bits, and receiving each received data corresponding to each received first signal level from the predetermined number of pattern data. 5. The data transfer method according to claim 2, wherein the data is restored using the corresponding pattern data. 7. The data transfer method according to claim 5, wherein the data transmission unit replaces the predetermined number of pattern data for the next processing with a current predetermined number of transmission data. 8. The data transfer method according to claim 6, wherein the data receiving unit replaces the predetermined number of pattern data for the next processing with a predetermined number of received data this time.