JP4400432B2 - Asynchronous FIFO packet communication device - Google Patents

Description

  The present invention relates to an asynchronous FIFO packet communication apparatus in which clock frequencies operating in a packet transmission side circuit and a reception side circuit are different from each other.

  Some communication devices that transmit and receive packets require asynchronous transfer with different clock frequencies that operate in the packet transmission side circuit and the reception side circuit. In such a communication apparatus, it is general to transfer packets via an asynchronous FIFO (First-In First-Out) between a transmission side circuit and a reception side circuit to synchronize different clock frequencies.

  In such a packet communication apparatus using an asynchronous FIFO, it is necessary for both the transmission side circuit and the reception side circuit of the packet to grasp the packet storage state of the asynchronous FIFO and the operation state of the other party. In order to exchange these with each other, a method has been used in which several signals are defined between the transmission side circuit and the reception side circuit and their state is transmitted to the other party. Here, since the clock frequencies operating in the transmission side circuit and the reception side circuit are different, a multi-stage flip-flop called a synchronizer is used as a method for synchronizing them. However, such a method using a synchronizer generally requires complicated control and circuit configuration, and it is difficult to perform efficient packet transfer.

  As a method for solving this, in addition to an asynchronous FIFO (hereinafter referred to as a data storage FIFO) for transferring the substance of data as disclosed in, for example, Japanese Patent Laid-Open No. 10-105375, the number of data to be written (or the number of data to be read) ) Is transferred using an asynchronous FIFO (hereinafter referred to as a data number storage FIFO). In this method, in addition to writing data to the data storage FIFO, the writing side writes the number of written data to the data number storage FIFO, and the reading side reads the number of written data from the data number storage FIFO, which corresponds to this data number. Read data from data storage FIFO. Since all transmission and reception side circuits including control signals are performed via an asynchronous FIFO, data transfer between different clocks can be easily and efficiently performed without using a synchronizer.

JP-A-10-105375

  When a conventional asynchronous FIFO buffer device having a data storage FIFO and a data number storage FIFO is applied to a packet communication device using a general-purpose communication protocol such as TCP / IP, the number of data stored in the data number storage FIFO is the packet length. Corresponding to For example, in the conventional packet communication device described in Japanese Patent Laid-Open No. 10-105375, when the number of data to be transferred is expressed in N bits, the data number storage FIFO has a configuration of N bits × M stages. On the other hand, in a general-purpose communication protocol such as TCP / IP, a field indicating the packet length is prepared in advance in the packet entity. For this reason, the packet length is redundantly stored in the two FIFOs of the data storage FIFO and the data number storage FIFO. For example, the field indicating the packet length in TCP / IP is 16 bits (in the case of IP) to 32 bits (in the case of TCP) when the packet length is represented in binary in byte units. Since this field is transferred redundantly for each packet, there is a problem that the circuit configuration is wasted and the scale thereof is increased.

  The present invention has been made to solve the above-described problems, and provides an asynchronous FIFO packet communication device that performs asynchronous transfer with a smaller circuit configuration without using a synchronizer that requires complicated control. The purpose is to do.

  Asynchronous FIFO packet communication apparatus according to the present invention includes a packet storage asynchronous FIFO (First-In First-Out) of K bits × L stages (both K and L are natural numbers) capable of asynchronously writing and reading packets, and the packet storage. A flag indicating that the packet has been stored in the asynchronous FIFO, and a readable 1-bit × M-stage (M is a natural number) packet storage notification asynchronous FIFO; a packet length register for storing the value of the packet length field of the received packet; And a packet is read from the packet storage asynchronous FIFO based on information read from the packet storage notification asynchronous FIFO and a value stored in the packet length register.

  A packet storage asynchronous FIFO (First-In First-Out) of K bits x L stages (both K and L are natural numbers) that can be written and read asynchronously, and a flag indicating that the packet is stored in the packet storage asynchronous FIFO 1 bit × M stage (M is a natural number) packet storage notification asynchronous FIFO, and a packet length register for storing the value of the packet length field of the received packet, and from the packet storage notification asynchronous FIFO Based on the read information and the value stored in the packet length register, by reading the packet from the packet storage asynchronous FIFO, the resources necessary for the FIFO are reduced, and the circuit necessary for the asynchronous FIFO packet communication is further reduced. Can be configured on a small scale.

Embodiment 1 FIG.
FIG. 1 is an explanatory diagram showing a configuration of a packet communication apparatus using an asynchronous FIFO according to the present invention. In FIG. 1, an asynchronous FIFO packet communication device 100 includes a packet storage asynchronous FIFO 101 that stores the substance of a packet to be transferred, a packet storage notification asynchronous FIFO 102 that notifies the packet storage state of the packet storage FIFO 101 from the input side to the output side, A write control circuit 103 that inputs a packet to the packet storage asynchronous FIFO 101 and writes a flag indicating that the packet is stored in the packet storage notification asynchronous FIFO 102; outputs a packet from the packet storage asynchronous FIFO 101; and outputs a packet from the packet storage notification asynchronous FIFO 102 And a read control circuit 104 that reads a flag indicating that the data is stored. In addition, a packet input signal 105 for inputting a packet, a packet output signal 106 for outputting a packet, a Full signal 107 indicating that the packet storage notification asynchronous FIFO 102 is full, and a write signal between the circuits. A Wen signal 108 for writing a flag indicating that the packet has been stored in the packet storage notification asynchronous FIFO 102 by the control circuit 103, and a Ren signal for reading the flag indicating that the read control circuit 104 has stored the packet from the packet storage notification asynchronous FIFO 102 109, an Empty signal 110 indicating that the packet storage notification asynchronous FIFO 102 is empty, a Status signal 111 indicating the amount of packets stored in the packet storage asynchronous FIFO 101, and the write control circuit 103 performs packet storage asynchronous F And Wen signals 112 for writing packets into FO101, is performed to input and output signals of Ren signal 113 for read control circuit 104 reads the packet from the packet storage asynchronous FIFO 101.

  The configuration of the packet storage asynchronous FIFO 101 in the first embodiment is K bits × L stages, and the configuration of the packet storage notification asynchronous FIFO 102 is 1 bit × M stages. Here, K, L, and M are integers of 1 or more. For example, in a communication protocol such as TCP / IP, K is generally 32 bits. L and M mainly depend on hardware resources to be implemented, communication protocol layers of packets to be transferred, and the like.

  FIG. 2 is an explanatory diagram showing the configuration of the write control circuit 103 in the asynchronous FIFO packet communication apparatus 100. In FIG. 2, the write control circuit 104 includes a counter 201 that counts the packet length in K-bit units, a packet length register 202 that stores the packet length, a comparison circuit 203 that compares the counter 201 and the packet length register 202, A Wen control circuit 204 that controls a write request signal Wen108 to the storage notification asynchronous FIFO 102 and a Wen control circuit 205 that controls a write request signal Wen112 to the packet storage asynchronous FIFO 101 are provided.

  FIG. 3 is an explanatory diagram showing the configuration of the read control circuit 104 in the asynchronous FIFO packet communication apparatus 100. In FIG. 3, a counter 301 that counts the packet length in K-bit units, a packet length register 302 that stores the packet length, a comparison circuit 303 that compares the counter 301 and the packet length register 302, and a packet storage notification asynchronous FIFO 102 A Wen control circuit 304 that controls the read request signal Ren109 and a Wen control circuit 305 that controls the read request signal Ren113 to the packet storage asynchronous FIFO 101 are provided.

  The operation of the asynchronous FIFO packet communication apparatus according to the first embodiment will be described below with reference to FIGS.

First, as a first step, before the input packet signal is input to the packet storage asynchronous FIFO 101, the write control circuit 103 checks the input packet signal.
When a packet is input to the input packet signal 105 in units of K bits, the write control circuit 103 increments the counter 201 by 1 and repeats this until the input of the packet is completed. In parallel with this, the write control circuit 103 reads the packet length field from the packet header and stores it in the packet length register 202. In general-purpose communication protocols such as TCP / IP, the position of the packet length field in the packet is fixed regardless of the packet length, and the counter 201 has a predetermined value for storing the packet length in the packet length register 202. It can be done when
Subsequently, the Wen control circuit 205 of the write control circuit 103 compares the status signal 111 indicating the packet storage amount of the packet storage asynchronous FIFO 101 with the value stored in the packet length register 202, and sends the packet to the packet storage asynchronous FIFO 101. Whether or not can be stored is determined. If the data can be stored, the Wen control circuit 205 of the write control circuit 103 validates the Wen signal 112 and stores the packet in the packet storage asynchronous FIFO 101. If the data cannot be stored, the Wen control circuit 205 of the write control circuit 103 invalidates the Wen signal 112, discards the packet, and waits for input of the next packet.

  When the packet can be stored in the packet storage asynchronous FIFO 101 and storage of the packet is started, the comparison circuit 203 of the write control circuit 103 determines whether or not the input of the packet to the packet storage asynchronous FIFO 101 is completed. Each time a K-bit packet is input, the counter 201 and the packet length register 202 are compared. When the comparison result from the comparison circuit 203 that the value of the counter 201 matches the value of the packet length register 202 is input, the Wen control circuit 205 determines that the input of the packet has been completed, and the Wen signal 112 is output. The input of the packet to the packet storage asynchronous FIFO 101 is stopped by invalidating. At the same time, when the comparison result from the comparison circuit 203 that the value of the counter 201 matches the value of the packet length register 202 is input, the Wen control circuit 204 sends the Wen signal 108 to the packet storage notification asynchronous FIFO 102 by one clock. Enable for minutes and output. When the Wen signal 108 becomes valid for one clock, 1-bit data of the input flag signal 114 is written to the packet storage notification asynchronous FIFO 102, which corresponds to the completion of storing one packet in the packet storage asynchronous FIFO 101. . Here, the input flag signal 114 is an arbitrary value fixed to 1 or 0. As long as the value of the counter 201 does not match the value of the packet length register 202, the write control circuit 103 continues incrementing the counter 201 and valid output of the Wen signal 112 by the Wen control circuit 205.

  Next, as a second step, the Ren control circuit 304 of the read control circuit 104 checks the Empty signal 110 and determines whether or not there is data written in the packet storage notification asynchronous FIFO 102, that is, the packet storage asynchronous FIFO 101 already has 1 in it. Determine whether more than one packet is stored. When the Empty signal is invalid (there is written data), since the packet is already stored in the packet storage asynchronous FIFO 101, the Ren control circuit 305 of the read control circuit 104 enables the Ren signal 113 and the packet storage is asynchronous. A packet is output from the FIFO 101.

  Subsequently, when a packet is output from the packet storage asynchronous FIFO 101 as an output packet signal 106 in units of K bits, the read control circuit 104 increments the counter 301 by 1, and repeats this until the output of the packet is completed. In parallel with this, the read control circuit 104 reads the packet length field from the packet header and stores it in the packet length register 302. As with the write control circuit 103, in a general-purpose communication protocol such as TCP / IP, the position of the packet length field in the packet is fixed regardless of the packet length, and the packet length is stored in the packet length register 302. It may be executed when the counter 301 reaches a predetermined value.

  Whether or not the output of the packet from the packet storage asynchronous FIFO 101 is completed is determined by the comparison circuit 303 of the read control circuit 104 using the value of the counter 301 and the value of the packet length register 302 every time a K-bit packet is output. Do by comparing. When the comparison result from the comparison circuit 303 that the value of the counter 301 matches the value of the packet length register 302 is input, the Ren control circuit 305 determines that the output of the packet has been completed and outputs the Ren signal 113. The packet output from the output packet signal 106 is stopped by invalidating the packet. At the same time, the Ren control circuit 304 validates and outputs the Ren signal 109 for one clock to the packet storage notification asynchronous FIFO 102. When the Ren signal 109 becomes valid for one clock, the 1-bit data of the output flag signal 115 is read from the packet storage notification asynchronous FIFO 102, which corresponds to the completion of reading one packet from the packet storage asynchronous FIFO 101. . Here, the output flag signal 115 is an arbitrary fixed value of 1 or 0 written by the write control circuit 103, that is, the input flag signal 114, but the Ren control circuit 304 discards it. As long as the value of the counter 301 does not match the value of the packet length register 302, the read control circuit 104 continues incrementing the counter 301 and valid output of the Ren signal 113.

  As described above, according to the present invention, the packet storage notification asynchronous FIFO 102 stores only 1-bit data indicating whether or not one or more packets are stored in the packet storage asynchronous FIFO 101. The packet storage status in the storage asynchronous FIFO 101 can be easily grasped, and the circuit necessary for asynchronous FIFO packet communication can be configured on a smaller scale. That is, according to the conventional technique, the N-bit × M-stage configuration of the data number storage asynchronous FIFO required for storing the packet length of the packet to be transferred can be realized by the 1-bit × M-stage configuration. By doing so, it is possible to reduce the resources necessary for the FIFO, and to configure a circuit necessary for the asynchronous FIFO packet communication on a smaller scale.

  In the first embodiment, the writing and reading operations for a single packet have been described. However, according to the present invention, even when the write control circuit 103 and the read control circuit 104 operate in parallel in the processing of a plurality of packets. Similar effects can be obtained.

Explanatory drawing which shows the structure of the packet communication apparatus using asynchronous FIFO Explanatory drawing which shows the structure of the write control circuit 103 in the asynchronous FIFO packet communication apparatus 100. Explanatory drawing which shows the structure of the read control circuit 104 in the asynchronous FIFO packet communication apparatus 100.

Explanation of symbols

100 Asynchronous FIFO packet communication device 101 Packet storage asynchronous FIFO
102 Packet storage notification asynchronous FIFO
103 Write Control Circuit 104 Read Control Circuit 105 Input Packet Signal 106 Output Packet Signal 107 Full Signal 108 Wen Signal 109 Ren Signal 110 Empty Signal 111 Status Signal 112 Wen Signal 113 Ren Signal 114 Input Flag Signal 115 Output Flag Signal 201 Counter 202 Packet Length Register 203 Comparison circuit 204 Wen control circuit 205 Wen control circuit 301 Counter 302 Packet length register 303 Comparison circuit 304 Ren control circuit 305 Ren control circuit

Claims (1)

A packet storage asynchronous FIFO (First-In First-Out) of K bits x L stages (both K and L are natural numbers) capable of asynchronously writing and reading packets;
A flag indicating that a packet has been stored in the packet storage asynchronous FIFO, and a readable 1 bit × M stage (M is a natural number) packet storage notification asynchronous FIFO;
A packet length register for storing the value of the packet length field of the received packet,
An asynchronous FIFO packet communication circuit, which reads a packet from the packet storage asynchronous FIFO based on information read from the packet storage notification asynchronous FIFO and a value stored in the packet length register.

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