JPS6155686B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device in a data processing device.

FIG. 1 is a diagram showing an example of a conventional storage device, and includes a buffer register 1 that temporarily stores data that is continuously sent from a host device, etc., and a buffer register 1 that specifies the storage address of this data. , and a storage circuit 3 that stores the data of the buffer register 1 at a storage address specified by the address register 2. That is, all the data that are successively and sequentially transferred from a host device or the like are sequentially stored at the address of the storage circuit 3 specified by the address register 2 while changing the specification of the address register 2 sequentially.

Figure 2 shows ABCC in buffer register 1 of Figure 1.
. . . shows the relationship between addresses and data when sequentially transferred data is sequentially stored in the storage circuit 3 starting from address 0. In general, data transferred from a host device, etc. depends on the nature of the data in units of transfer (e.g. bytes, etc.).
It is rare for different bytes to be transferred for each transfer (described below in units of bytes). For example, when considering the transfer of data such as an address book, it is necessary to divide the fields into two fields, the name field and the address field, and uniformly secure the expected maximum number of bytes for each field, leaving all bytes other than the actual valid number of bytes blank. It is usually filled in by a code or the like. That is, the appearance rate of consecutive identical bytes is very high in parts other than effective bytes.

An object of the present invention is to reduce the storage capacity of a storage circuit based on the above considerations.

According to the present invention, in a storage device having a storage means for sequentially storing continuously transferred data for each transfer unit, and an addressing means for specifying a storage address of the data, at least two transfer units are stored. a detection means for outputting a first detection signal when the same data is transferred continuously; and a detection means for outputting a second detection signal when at least three transfer units of the same data are transferred continuously; a counting means for counting the number of transfer units in which the same data is continuously transferred in response to the first detection signal;
count holding means that holds the contents of the counting means at the time when the detection signal of the data is no longer output; and special code generating means that generates a special code that is different from any data that is continuously transferred;
While the second detection signal is not output, the continuously transferred data is sent to the storage means while sequentially changing the contents of the addressing means, and when the second detection signal is output; After sending one of the same data to the storage means, the contents of the special code generation means are sent to the storage means as the next data, and the contents of the count holding means are sent as the next data to the storage means. The present invention provides a storage device characterized in that the data transmission control means is configured to compress and store data to be stored.

The present invention will be described in detail below with reference to the drawings.

Fig. 3 is a conceptual diagram of the present invention, where 10 is a buffer register that temporarily stores data transferred from a host device, etc., and 11 is a data compression register that detects continuous data, compresses it, and outputs it. An encoder 12 is a buffer register 1 that temporarily stores data compressed by the encoder 11.
Reference numeral 3 indicates an address register for specifying the address of the memory circuit, and reference numeral 14 indicates a memory circuit for storing the contents of the buffer register 12 at the address specified by the address register 13.

FIG. 4 shows the relationship between addresses and data when the data in FIG. 2 is stored in the storage circuit 14 through the encoder 11 in FIG. 3. That is, data corresponding to addresses 0, 1, 2, etc. is A,
B, C, etc. are stored sequentially. In particular, C5 stored corresponding to addresses 2, 3, and 4 has a special meaning indicating that data in which CCCCC and C are repeated five times is compressed and stored. Similarly, address 5,
This shows that data in which D4DDDD and D continue four times, which are stored corresponding to numbers 6 and 7, are compressed and stored.

FIG. 5 is a diagram showing an embodiment of a block diagram showing details of the encoder 11 for data compression in the storage device of FIG. 3 according to the present invention.

100 to 102 are buffer registers for storing data, 103 to 105 are flip-flops for control, and 106 are buffer registers 100 and 101.
A comparison circuit 1 detects whether the contents of the two buffer registers match by comparing the outputs of the two buffer registers.
07 is a comparison circuit that compares the outputs of buffer registers 100 to 102 and detects whether the contents of the three buffer registers match; 108 is a comparison circuit that compares the outputs of buffer registers 100 to 102;
109 is a counter register that temporarily holds the contents of counter 108. 110 is a special code generation circuit that generates the symbol shown in FIG. 4 (the symbol never appears in the input data). , 11 to 114 are AND gate circuits, 115 to 118 are inhibit gate circuits, 119 and 120 are OR gate circuits, and 121
122 is a buffer register for temporarily storing data to be stored in the memory circuit 121; 123 is a memory circuit;
is an address register that specifies the address of the memory circuit 121, and the contents of the address register 123 can be sequentially changed according to the output from the OR gate circuit 120.

FIG. 6 shows buffer registers 100 to 102 and flip-flops 103 to 102 of FIG. 5 for the clock.
105, counter 108, counter register 10
9 is a diagram showing how the contents of buffer register 122 and address register 123 change over time.

The operation shown in FIG. 5 will be explained below using FIG. 6.

First, the operations of buffer registers 100-102 will be explained. At clock 0, A is input as data to the buffer register 100, and at clocks 1, 2, 3, etc., B, C,
C...... is input. In synchronization with this, the contents of buffer register 100 are transferred to buffer register 101 with a delay of one clock. Similarly, the contents of buffer register 101 are transferred to buffer register 102 with a one clock delay.

Next, the operation of flip-flops 103-105 will be explained. Buffer register 100-10
When all the contents of 2 match, a flip-flop 103 is set upon receiving a detection signal 107 (this is called a second detection signal although the order is reversed). In Figure 6, clocks 4 to 6 and clock 9,
10 corresponds to this. The contents of flip-flop 103 are transferred to flip-flop 104 with a one clock delay in synchronization with the clock. Similarly, flip-flop 105 and flip-flop 10 are connected to flip-flop 105.
The contents of 4 are transferred.

Next, the operation of the counter 108 will be explained.
The counter 108 stores 1 as an initial value, and when the contents of the buffer registers 100 and 101 match, it receives a detection signal 106 (this will be referred to as a first detection signal) and is incremented by 1. That is, at clocks 3 to 6, data C is stored in buffer registers 101 and 102, and the counter 108 is sequentially added up to 5 at clock 6. As shown by clock 7, if the contents of buffer registers 100 and 102 do not match and comparison circuit 106 does not output the first detection signal, the initial value is returned.

Next, the operation of counter register 109 will be explained. The counter register 109 stores the contents of the counter 108 one clock ago when the flip-flop 103 becomes "0" and the flip-flop 104 becomes "1", that is, when the AND gate circuit 111 is opened by the output of the inhibit gate circuit 115. Transport and temporarily store. This value indicates the number of consecutive times the same data is displayed. That is, data C at clock 7.
The number of consecutive times 5 of data D is stored in the clock 11, and the number 4 of consecutive times data D is stored in the clock 11. Note that the contents of clocks 0-6 are determined by the previous state.

Next, the operation related to buffer register 122 will be explained. The buffer register 122 has 3
Data is input from two routes. That is, the contents of the buffer register 102 are input through one AND gate circuit 113, and the contents of the count register 109 are input through the other AND gate circuit 112.
The contents of the special code generation circuit 110 are inputted through another AND gate circuit 114. These AND gate circuits are opened by inhibit gate circuits 116-118 under conditions depending on the contents of flip-flops 103-105. That is, in clocks 2 to 4, the AND gate circuit 113 is opened by the output of the inhibit gate circuit 117, so that 1 is output.
The contents of the buffer register 102 are transferred to the buffer register 122 with a clock delay, and the contents of the buffer register 102 are transferred to the buffer register 122 after a clock delay.
Then, the AND gate circuit 114 is opened by the output of the inhibit gate circuit 118, and the contents of the special code generation circuit 110 are transferred to the buffer register 122 with a delay of one clock, and the output of the inhibit gate circuit 116 is transferred at clock 8. When the AND gate circuit 112 is opened, the contents of the counter register 109 are transferred to the buffer register 122 with a delay of one clock.

Finally, address register 123 and memory circuit 12
The data stored in 1 will be explained. In the address register 123, the contents of the address register 123 are sequentially changed in synchronization with the timing of setting data in the buffer register 122, and the contents of the buffer register 122 are sequentially stored in the storage circuit 121 at the designated address. That is, data is set in the buffer register 122 by the outputs of the inhibit gate circuits 116 to 118, and at the same time, the addressing of the address register 123 is sequentially changed through the OR gate circuit 120.
In FIG. 6, when the initial value of the address register 123 is 0, addresses 0, 1, 2, 3, 4...
It is shown that contents A, B, C, , 5, . . . are stored in the buffer register 122 in response to . That is, when the data in FIG. 2 is input as the input data in FIG. 5, the data is compressed and stored in the storage circuit 121 as shown in FIG.

As is clear from the above description, the present invention has the effect of significantly reducing the capacity of the memory circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a conventional storage device, FIG. 2 is a diagram showing the relationship between data and addresses in the storage device of FIG. 1, and FIG. 3 is a conceptual diagram of the present invention. 4 is a diagram showing the relationship between data and addresses in the storage device of FIG. 3, FIG. 5 is a diagram showing one embodiment of the present invention in blocks, and FIG. 6 is a diagram showing each register in FIG. 5. It is a diagram showing the state transition of. Explanation of symbols: 1 is a buffer register, 2 is an address register, 3 is a memory circuit, 10 is a buffer register, 11 is an encoder, 12 is a buffer register, 13 is an address register, 14 is a memory circuit, 100 to 102 are Battle register, 103
-105 are flip-flops, 106 and 107 are comparison circuits, 108 is a counter, 109 is a counter register, 110 is a special code generation circuit, 111
114 to 114 are AND gate circuits, 115 to 118 are inhibit gate circuits, 119 and 120 are OR gate circuits, 121 is a memory circuit, 122 is a buffer register, and 123 is an address register.

Claims (1)

[Claims] 1. In a storage device having storage means for sequentially storing continuously transferred data for each transfer unit, and addressing means for specifying the storage address of the data, at least two transfer units of the same data are stored consecutively. a detection means that outputs a first detection signal when the same data is transferred in succession, and outputs a second detection signal when at least three transfer units of the same data are transferred in succession; a counting means for counting the number of transfer units in which the same data has been continuously transferred; a count holding means for holding the contents of the counting means at the time when the second detection signal is no longer output; and special code generating means for generating a special code different from any data transferred as a first detection signal; The data is sent to the storage means while changing the second
When a detection signal is output, one of the same data is sent to the storage means, and then the contents of the special code generation means are sent to the storage means as the next data, and the count is held as the next data. A storage device comprising data sending control means configured to send the contents of the means to the storage means, and compressing and storing data to be stored.